The Library
A formal theory of railway track networks in higher-order logic and its applications in interlocking design
Tools
Tools
Tools
Wong, Wai (1992) A formal theory of railway track networks in higher-order logic and its applications in interlocking design. PhD thesis, University of Warwick.
|
PDF
WRAP_Theses_Wong_1992.pdf - Submitted Version - Requires a PDF viewer. Download (5Mb) | Preview |
Official URL: http://webcat.warwick.ac.uk/record=b3251632~S15
Abstract
The research described in this dissertation centres on the application of a discipline of formal methods in railway signalling system design. A generic abstract model of railway track networks and signals has been developed in Higher-Order Logic(HOL). It consists of several theories arranged in a hierarchy. Railway track networks are modelled by a class of constraint labelled directed graphs. HOL theories of graphs and paths have been developed for representing track networks. HOL theories modelling individual track components and signals have also been developed. These theories are then combined to create a theory of track network. Three applications of this model are described. The first is a network verifier which verifies a formal specification of track layout against its abstract model by proving theorems automatically. The second application is to extract information from the specifications and to create control tables automatically. Lastly, a method of modelling the interlocking processor using finite state machines is described. Although this research has centred on railway signalling, it can be viewed as a case study of how to apply formal methods in the analysis and design of safety- critical systems. The approach and methods used can be generalized in order to be useful in other industries.
| Item Type: | Thesis (PhD) | ||||
|---|---|---|---|---|---|
| Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TF Railroad engineering and operation |
||||
| Library of Congress Subject Headings (LCSH): | Railroads -- Signaling, Formal methods (Computer science) | ||||
| Official Date: | 1992 | ||||
| Dates: |
|
||||
| Institution: | University of Warwick | ||||
| Theses Department: | Department of Engineering | ||||
| Thesis Type: | PhD | ||||
| Publication Status: | Unpublished | ||||
| Supervisor(s)/Advisor: | Cullyer, W. J. | ||||
| Extent: | xii, 296 leaves : illustrations | ||||
| Language: | eng |
Request changes or add full text files to a record
Repository staff actions (login required)
 |
View Item |
Downloads
Downloads per month over past year
