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Deep p-ring trench termination : an innovative and cost-effective way to reduce silicon area
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Antoniou, M., Lophitis, N., Udrea, F., Rahimo, M., Vemulapati, U., Corvasce, C. and Badstuebner, U. (2019) Deep p-ring trench termination : an innovative and cost-effective way to reduce silicon area. IEEE Electron Device Letters, 40 (2). pp. 177-180. doi:10.1109/LED.2018.2890702
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Official URL: http://dx.doi.org/10.1109/LED.2018.2890702
Abstract
A new type of high voltage termination, namely the “deep p-ring trench” termination design for high voltage, high power devices is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required, it also removes the need for an additional mask as is the case of the traditional p+ ring type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide which results in reduced hot carrier injection and improved device reliability
| Item Type: | Journal Article | ||||||
|---|---|---|---|---|---|---|---|
| Divisions: | Faculty of Science > Engineering | ||||||
| Journal or Publication Title: | IEEE Electron Device Letters | ||||||
| Publisher: | IEEE | ||||||
| ISSN: | 0741-3106 | ||||||
| Official Date: | 3 January 2019 | ||||||
| Dates: |
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| Volume: | 40 | ||||||
| Number: | 2 | ||||||
| Page Range: | pp. 177-180 | ||||||
| DOI: | 10.1109/LED.2018.2890702 | ||||||
| Status: | Peer Reviewed | ||||||
| Publication Status: | Published | ||||||
| Access rights to Published version: | Restricted or Subscription Access | ||||||
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