UNSPECIFIED (2000) Novel pattern-based power estimation tool with accurate glitch modeling EMERGING TECHNOLOGIES FOR THE 21ST CENTURY. In: IEEE International Symposium on Circuits and Systems (ISCAS 2000), MAY 28-31, 2000, GENEVA, SWITZERLAND.

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Abstract

In this paper an enhanced gate-level power estimation tool with efficient glitch modeling is presented. With little addition in computational cost from the traditional even driven simulation the new technique employs better delay modeling of glitch peaks through the introduction of glitch coefficients and appropriate glitch filtering to achieve improvement in accuracy. The simulator is shown to reduce the estimation error by up to 50% from the traditional toggle-based technique, and has accuracy within 10% of SPICE. The simulator post-processes Verilog-XL output, the overall run-time is better than SPICE by more than an order of magnitude.

Item Type:	Conference Item (UNSPECIFIED)
Subjects:	Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TK Electrical engineering. Electronics Nuclear engineering
Journal or Publication Title:	ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV
Publisher:	IEEE
ISBN:	*************
Date:	2000
Number of Pages:	4
Page Range:	pp. 721-724
Publication Status:	Published
Title of Event:	IEEE International Symposium on Circuits and Systems (ISCAS 2000)
Location of Event:	GENEVA, SWITZERLAND
Date(s) of Event:	MAY 28-31, 2000
URI:	http://wrap.warwick.ac.uk/id/eprint/12686

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