SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide
UNSPECIFIED (2000) SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 15 (2). pp. 135-138. ISSN 0268-1242Full text not available from this repository.
An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer. The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.
|Item Type:||Journal Article|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering
T Technology > TA Engineering (General). Civil engineering (General)
Q Science > QC Physics
|Journal or Publication Title:||SEMICONDUCTOR SCIENCE AND TECHNOLOGY|
|Publisher:||IOP PUBLISHING LTD|
|Number of Pages:||4|
|Page Range:||pp. 135-138|
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