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SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide
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UNSPECIFIED. (2000) SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 15 (2). pp. 135-138. ISSN 0268-1242
Full text not available from this repository.Abstract
An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer. The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.
| Item Type: | Journal Article | ||||
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| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering T Technology > TA Engineering (General). Civil engineering (General) Q Science > QC Physics |
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| Journal or Publication Title: | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | ||||
| Publisher: | IOP PUBLISHING LTD | ||||
| ISSN: | 0268-1242 | ||||
| Official Date: | February 2000 | ||||
| Dates: |
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| Volume: | 15 | ||||
| Number: | 2 | ||||
| Number of Pages: | 4 | ||||
| Page Range: | pp. 135-138 | ||||
| Publication Status: | Published | ||||
| URI: | http://wrap.warwick.ac.uk/id/eprint/13651 |
Data sourced from Thomson Reuters' Web of Knowledge
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