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Power minimisation of VLSI wave digital filters through systolic block size selection

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UNSPECIFIED (1999) Power minimisation of VLSI wave digital filters through systolic block size selection. ELECTRONICS LETTERS, 35 (21). pp. 1795-1796.

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Abstract

An investigation into systolic architectures for wave digital filters for low-power applications is presented. Based on a three-port adaptor implementation of the second-order section, minimum power is found using pipelining with a 2 bit block size for which the power consumption is reduced by 50% and the power-area-delay performance increased by 5 times relative to the starting, non-pipelined, implementation.

Item Type: Journal Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Journal or Publication Title: ELECTRONICS LETTERS
Publisher: IEE-INST ELEC ENG
ISSN: 0013-5194
Official Date: 14 October 1999
Dates:
DateEvent
14 October 1999UNSPECIFIED
Volume: 35
Number: 21
Number of Pages: 2
Page Range: pp. 1795-1796
Publication Status: Published

Data sourced from Thomson Reuters' Web of Knowledge

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