Performance evaluation of a bus-based multistage multiprocessor architecture
UNSPECIFIED (2000) Performance evaluation of a bus-based multistage multiprocessor architecture. JOURNAL OF SYSTEMS ARCHITECTURE, 46 (1). pp. 39-47. ISSN 1383-7621Full text not available from this repository.
This paper proposes and evaluates a class of interconnection networks, which provide performance comparable to a multiple bus network with considerably lower cost. These networks, referred to as hybrid networks, are formed by beginning with a multistage network and substituting buses in the second stage. Analytic models are developed to evaluate the performance of the system, The analysis includes both uniform and non-uniform distribution of requests. The results obtained are compared with simulation results. (C) 2000 Elsevier Science B.V. All rights reserved.
|Item Type:||Journal Article|
|Subjects:||Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software|
|Journal or Publication Title:||JOURNAL OF SYSTEMS ARCHITECTURE|
|Publisher:||ELSEVIER SCIENCE BV|
|Date:||1 January 2000|
|Number of Pages:||9|
|Page Range:||pp. 39-47|
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