Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal-oxide-semiconductor field effect transistor channels
UNSPECIFIED. (1999) Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal-oxide-semiconductor field effect transistor channels. APPLIED PHYSICS LETTERS, 74 (13). pp. 1848-1850. ISSN 0003-6951Full text not available from this repository.
Si/Si0.64Ge0.36/Si heterostructures have been grown at low temperature (450 degrees C) to avoid the strain-induced roughening observed for growth temperatures of 550 degrees C and above. The electrical properties of these structures are poor, and thought to be associated with grown-in point defects as indicated in positron annihilation spectroscopy. However, after an in situ annealing procedure (800 degrees C for 30 min) the electrical properties dramatically improve, giving an optimum 4 K mobility of 2500 cm(2) V-1 s(-1) for a sheet density of 6.2 x 10(11) cm(-2). The low temperature growth yields highly planar interfaces, which are maintained after anneal as evidenced from transmission electron microscopy. This and secondary ion mass spectroscopy measurements demonstrate that the metastably strained alloy layer can endure the in situ anneal procedure necessary for enhanced electrical properties. Further studies have shown that the layers can also withstand a 120 min thermal oxidation at 800 degrees C, commensurate with metal-oxide-semiconductor device fabrication. (C) 1999 American Institute of Physics. [S0003-6951(99)03213-1].
|Item Type:||Journal Article|
|Subjects:||Q Science > QC Physics|
|Journal or Publication Title:||APPLIED PHYSICS LETTERS|
|Publisher:||AMER INST PHYSICS|
|Official Date:||29 March 1999|
|Number of Pages:||3|
|Page Range:||pp. 1848-1850|
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