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Partial SOI as a HV platform technology for Power Integrated Circuits
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Holke, Alexander, Antoniou, Marina and Udrea, Florin (2020) Partial SOI as a HV platform technology for Power Integrated Circuits. In: 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vienna, Austria, 13 Sep - 18 Sep 2020 pp. 435-438. ISBN 978-1-7281-4837-3. ISSN 1063-6854. doi:10.1109/ISPSD46842.2020.9170051
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Official URL: http://dx.doi.org/10.1109/ISPSD46842.2020.9170051
Abstract
Partial SOI (PSOI) is revisited as a suitable High Voltage (HV) architecture for Power Integrated Circuits (PICs). The added process complexity compared to SOI RESURF is offset by the better heat conduction due to thinner BOX, the wider voltage range capability and the reduced parasitic capacitance to the Handle Wafer (HW). The new proposed platform technology is therefore particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low Ron, fast switching and reduced self-heating are essential. This work reports on the extension of a 200V PSOI process to 400V while providing competitive Ron and low HCI degradation.
| Item Type: | Conference Item (Paper) | ||||||
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| Divisions: | Faculty of Science > Engineering | ||||||
| Publisher: | IEEE | ||||||
| ISBN: | 978-1-7281-4837-3 | ||||||
| ISSN: | 1063-6854 | ||||||
| Book Title: | 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) | ||||||
| Official Date: | 2020 | ||||||
| Dates: |
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| Page Range: | pp. 435-438 | ||||||
| DOI: | 10.1109/ISPSD46842.2020.9170051 | ||||||
| Status: | Peer Reviewed | ||||||
| Publication Status: | Published | ||||||
| Access rights to Published version: | Restricted or Subscription Access | ||||||
| Conference Paper Type: | Paper | ||||||
| Title of Event: | 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) | ||||||
| Type of Event: | Conference | ||||||
| Location of Event: | Vienna, Austria | ||||||
| Date(s) of Event: | 13 Sep - 18 Sep 2020 |
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