A Compact Trench-Assisted Space-Modulated JTE Design for High-Voltage 4H-SiC Devices

This article proposes a compact trench-assisted space-modulated junction termination extension (TSM-JTE) design for high-voltage 4H-silicon carbide (SiC) devices. In this design, trench structures are introduced into the JTE region to effectively split the termination region into three functional zones. The proposed termination structure is cost effective in terms of the chip area it occupies; for devices rated at 10 kV, the termination structure extends the edge of the device by only <inline-formula> <tex-math notation="LaTeX">$250~\mu \text{m}$ </tex-math></inline-formula>. Requiring only one implant, it is relatively cheap to fabricate, while a wide implantation dose window endures that is relatively insensitive to variations in dose that may occur during processing. The same advantages occur at 20 kV, the TSM-JTE proving to have the best tradeoff between maximum breakdown voltage and implantation window, compared with other single implant termination designs, achieving this in <inline-formula> <tex-math notation="LaTeX">$500~\mu \text{m}$ </tex-math></inline-formula> of termination length. At 3.3 kV, a 110-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> TSM-JTE retains its advantages over the other JTE designs, but floating field rings are expected to consume less area, though this is not the case at the higher voltages.


I. INTRODUCTION
T HE superior electrical and thermal properties of silicon carbide (SiC) have made it an excellent candidate for high power applications. 4H-SiC devices rated above 10 kV are an attractive prospect for grid applications, in order to reduce the number of devices required in, for example, voltage-source converters. The realization of these high-voltage devices is based on the continual improvement in the epitaxial growth of thick 4H-SiC (>100 µm), with a marked improvement in defect densities [1]; however, the starting wafers remain expensive. As a result, in order to reduce device cost, it is important to maximize device yield and to minimize the area given over to the termination region. The termination region surrounds the perimeter of a power device chip's active, current carrying central region. Its primary purpose is to alleviate the electric field at the edge of a device, so maximizing the breakdown voltage. However, if the termination is not optimized, breakdown can occur prematurely. This termination region can also be very large, accounting for a large proportion of a chip. Therefore, the following principles must be applied in designing the device's termination: First, the termination must be effective, maximizing the breakdown voltage. Second, its fabrication should be manufacturable and repeatable. This requires a wide implantation dose window for a Junction termination extension (JTE) termination in order to counter variations in dose that can occur between wafers, or wafer lots. Third, to lower costs, the termination should use minimal semiconductor area, requiring a small termination length, L term . Fourth, a minimum number of expensive implant steps should be used.
Floating field ring (FFR) termination is an effective and repeatable design choice at lower voltages, but the chip area they occupy in high-voltage designs is relatively large. A 27-kV 4H-SiC IGBT was reported in 2014 [2], a proof of concept device that used a conventional FFR design that extended the active area by 1500 µm radially, occupying 65% of the 20-A chip area. A more optimized design for 14-kV 4H-SiC p-i-n diode was fabricated [3] with an advanced multiple expansion ratio FFR termination. While this design was 99% efficient, it required a termination length of 720 µm. JTE is another popular option that attracts attention due to the small chip area requirement at high voltage. Implanted single-zone JTE (SZ-JTE) and multizone JTE (MZ-JTE) structures with and without etched steps have been studied extensively [4], [5], while advanced structures such as space-modulated JTE (SM-JTE) and multiple-floating-zone JTE (MFZ-JTE) have been shown to simplify the fabrication process and reduce the implantation cost [4], [6]. In [4], a 15-kV SM-JTE design achieves a wide implantation window (±56% above 10 kV), using a single implant in 600 µm of extension. In [6], a 10-kV MFZ-JTE was produced in 450 µm of extension with a considerable implantation window (±41% above 8 kV) compared with conventional SZ-JTE. The design in this article is based on similar principles to the etched JTE with FFRs and middle rings presented in [7]. In this, a 200-µmlong JTE design, optimized for 15-kV devices, was shown to offer an effective solution with a relatively wide implantation window. Elsewhere, two novel single implant designs have been proposed. A tapered JTE design targeting at 6 kV [8], produced using greyscale photolithography, is >90% efficient, and occupies 250 µm. In [9], an intricate 120 zone JTE is produced utilizing a single mask and a single implant that achieved a breakdown voltage of 12 kV, with termination length over 500 µm.
The trench-assisted space-modulated JTE (TSM-JTE) structure introduced in this article is designed to minimize chip area for SiC devices rated to 10 kV and higher. Its novelty lies in the use of space-modulated regions, created by a single implant and a single trench etch into these, making it cheap to produce with a wide implantation window, as well as maximizing the breakdown. This study focuses initially on the development of the TSM-JTE and its optimization at 10 kV, while the results of structures optimized for 20-and 3.3-kV devices are also presented.

II. SIMULATION METHODOLOGY
The TSM-JTE structure proposed in this article is shown in Fig. 1. This structure, and the other structures in this article, were simulated and optimized using TCAD Silvaco. The proposed structure is notionally at the edge of a MOSFET (as in [10]), though the design is applicable to p-i-n diodes [4], [6], [7] and IGBTs [11].
Initially, this structure is optimized for a 10-kV device, using an epitaxial drift region with a width (W D ) of 100-µm layer and a doping of 3.5 × 10 14 cm −3 , grown upon an N + (1 × 10 19 cm −3 ) substrate. This structure has a theoretical (1-D) maximum breakdown voltage of 15 kV. Both the p-body depth and the JTE depth (d JTE ) are 700 nm, presuming a box profile implant. The doping of the JTE region, determined by the implantation dose, is varied in the simulations in order to determine the maximum possible breakdown voltage (V BD ) and the implantation window. The implantation window reported is the maximum percentage error in the dose that will maintain the target V BD . The proposed TSM-JTE design is benchmarked to SZ-JTE, SM-JTE, and MFZ-JTE designs, each of which is fabricated with only one implantation step.
The new TSM-JTE design comprises of several trench structures etched into the JTE region with controlled depth (d trench ), width, and spacing. This effectively splits the JTE region into three functional zones, which greatly widens the implantation dose window, just as in a MZ-JTE design, except with only one region of implantation. The structure in Fig. 1, when optimized for 10 kV, has 12 trenches etched into the JTE region and filled with silicon dioxide. The outermost trench is 130 µm wide while the 11 narrow trenches are all 2 µm wide. The space between the wide trench and the outermost narrow trench is 2 µm, with the space to each consecutive small trench incrementing by 1 µm (e.g., 3, 4, and 5 µm) every step closer to the center of the device. Five SM-JTE rings are located at the end of termination region which forms Zone 3 in Fig. 1. Their pitch (the sum of the ring width and space) is fixed at 10 µm. The initial ring space starts at 3 µm, increasing by 1 µm per ring space. The target total termination length L term for the 10-kV devices is 250 µm, just 2.5× the drift region width.

A. TSM-JTE Optimization
To understand the TSM-JTE, it is important to trace its development. The primary motivation for the work was to improve the design of termination structures that require only one implant, in order to reduce fabrication cost. As a result, the optimization started with a conventional SZ-JTE (L term = 250 µm) as a reference. This is T1 in Fig. 2(a). Its breakdown voltage and process window are plotted in Fig. 2(b) and summarized in Table I. Quite evidently, an SZ-JTE is not appropriate for high-voltage termination design due to a peak V BD of just 9.6 kV and an extremely narrow process window.
The optimization begins in T2 by etching the wide trench structure into the JTE region, to a depth, d trench , 400 nm from the surface. This simple modification significantly enhances the breakdown voltage, to a peak of 13.3 kV, 89% of the  ideal maximum. The implantation window, at 10 kV, is also improved, to ±33%, due to the space modulation effect of the trench, which leads to a near flat tail in the breakdown voltage versus dose curve. However, the window for achieving the peak breakdown voltage is relatively narrow, just ±10% at 12 kV.
When the dose is above 0.9 × 10 13 cm −2 the breakdown voltage of T2 structure decreases rapidly. In Fig. 3(a), the electric field distribution of a T2 structure with a dose of 1.1 × 10 13 cm −2 is plotted at a reverse voltage of 10 kV. Here, the location of the breakdown can be seen, at the bottom-left corner of the wide trench, where there is an abrupt change in the geometry. The electric field crowding at this point limits the breakdown voltage for T2.
To relieve the field at the inside edge of the wide trench, the 11 small trenches are inserted to the left of the wide trench, with expanding space between them, resulting in layout T3. The technique used here for spreading the electric field is like an FFR design, though the expansion of the spacing between the trenches is contrary to FFRs, the trench spacing expanding toward the center from right to left. The dose-V BD profile of T3 is improved from T2, having a much higher average breakdown voltage, the peak of which is 14.2 kV, and a window of ±19% at 12 kV. It is also clear from Fig. 3 that the electric field at the bottom-left corner of the wide trench has been distributed between the trenches and the peak electric field reduced.
Finally, the addition of the five space-modulated floating JTE rings to the end of the JTE termination leads to the proposed TSM-JTE design, T4 in Fig. 2. This greatly widens the process window, to ±37%, by smoothing out the second electric field peak located at 250 µm in Fig. 3 (the outer edge of the wide trench), which was responsible for breakdown at doses above 1.3 × 10 13 cm −2 .
In summary, in the full structure shown in Fig. 1, zones 2 and 3 provide the double space modulation, while zone 1 is mainly responsible for electric field smoothing. The results from all the simulations in Fig. 2 are summarized in Table I.

B. Trench Depth Optimization and Benchmarking
The trench depth, d trench , is a critical parameter for the TSM-JTE structure. In Fig. 4 and Table I, simulation results are presented in which d trench is varied from 300 to 500 nm, while the JTE depth is maintained at 700 nm. In the same figure, the proposed TSM-JTE is benchmarked to optimized SZ-JTE, SM-JTE, and MFZ-JTE structures, all of which are illustrated in Fig. 4(a). The JTE implanted region of the SM-JTE structure is the same as that used in the TSM-JTE. The simulated MFZ-JTE structure has 36 JTE zones with a fixed pitch (ring width and space), p, of 7 µm per zone. The starting space, s 1 , is set to 2 µm, with an expansion ratio of 1.02 (s n+1 = 1.02s n ). The results of the SZ-JTE are plotted again for benchmarking.
The SM-JTE structure achieves a peak breakdown voltage of 94% of the 15 kV maximum, but with a very narrow window. The MFZ-JTE structure offers a larger process window of ±27% at 10 kV, but with a significant reduction of the peak breakdown voltage, down to 82% of the maximum. The center of the process window increases from 9 × 10 12 to 1.6 × 10 12 cm −2 when an MFZ-JTE is used in place of an SM-JTE. This is due to the enhanced space modulation effect for the MFZ-JTE, where the effective dose is reduced across the entire termination area. There is a close relationship between the SM-JTE and MFZ-JTE. SM-JTE can be treated as an MFZ-JTE with the first grounded JTE being much larger; according to the same principle, MFZ-JTE can be treated as an SM-JTE with the space modulation expanding all the way toward the p-base transition region. Both designs rely on the space modulation effect. However, none of the conventional one-implant termination designs simulated herein could be optimized to reach the peak V BD or window of the TSM-JTE designs. From Fig. 4(b), the TSM-JTE design with a d trench of 300 nm offers the highest breakdown voltage of up to 96% of the maximum. However, its process window of ±29% at 12 kV can be improved to ±37% when d trench is increased to 400 nm, with the peak breakdown voltage dropping to 93%. Further increasing d trench to 500 nm causes a further reduction of the peak V BD to 87% of the maximum, but facilitates a very large process window of ±56% at 10 kV.
A trend can be observed across the three TSM-JTE structures, with the process window widening and the peak V BD dropping as d trench increases. The reason for this is as follows: As d trench increases, the effective dose in Zones 2 and 3 reduces. A greater JTE dose is, therefore, required for these two regions to reach their maximum V BD . However, the V BD peak of Zone 1 is less affected by trench depth and its peak remains at the same dose. With a d trench of 300 nm, the peak V BD of all three zones occurs at the same dose, resulting in its large, narrow peak observed in Fig. 4. As d trench increases and the peak voltage associated with Zones 2 and 3 shifts to higher dose, so the process window broadens and the maximum voltage reduces. A d trench of 500 nm is an extreme case in which the two peaks associated with Zone 1, and Zones 2 and 3 have shifted apart so far that there is a significant dip in the breakdown voltage in the center of the process window. This results in the two very narrow peaks at 12 kV. As a result, the TSM-JTE structure with a trench depth of 400 nm offers the best tradeoff between the V BD and the process window. However, with a well trialed, controlled implantation process, the use of the TSM-JTE with a trench depth of 300 nm may be preferred.
While this article has focused on the simulation of these structures, the fabrication of the proposed TSM-JTE structure is relatively simple. It adds one extra photolithography and dry etching step after the JTE is implanted. The extra fabrication process is much cheaper compared with ion implantation. The trench depth must be controlled between 400 and 500 nm (preferably close to 400 nm), which can be achieved by the accurate tuning of the dry etching process.

C. Optimizing the TSM-JTE Design for 20-kV Devices
The applicability of the TSM-JTE design has been investigated for even higher voltage devices (>20 kV). In this section, the n-drift region doping is 2.3 × 10 14 cm −3 with a thickness, W D of 186 µm. This has a theoretical maximum of 25.8 kV.
The same material parameters have been used in published work previously [12], in which the JTE used was a two-Zone SM-JTE with an L term of 600 µm. Here, we shall use the new TSM-JTE to reduce this to 500 µm, while only one implantation will be used, reducing the fabrication cost.
The JTE implanted region of the SM-JTE structure is the same as that used in the TSM-JTE. The simulated MFZ-JTE structure has 50 JTE zones with a pitch of 10 µm for each zone. The starting space is set to 2 µm, and the expansion ratio for the spaces is 1.026.
At 20 kV, the TSM-JTE structure comprises of 17 small trenches and one wide trench. As before, the trench spacing between the wide trench and the first small trench is 2 µm with every consecutive space 1 µm wider than the last. The wide trench is 160 µm wide. Four SM-JTE rings are located at the end of the termination region with ring width fixed at 3 µm and ring space starts at 3 µm and expands by 1 µm per ring. The trench depth remains 400 nm.
The results are shown in Fig. 5 and summarized in Table II. Just as at 10 kV, the similar SM-JTE and MFZ-JTE structures have a high V BD but a narrow window. In contrast, the proposed TSM-JTE design offers the best V BD (24.3 kV; 92% of maximum) and a process window of ±32% at 20 kV, therefore, offering a high likelihood of achieving the targeted breakdown voltage.

D. Optimizing the TSM-JTE Design for 3.3-kV Devices
Although the TSM-JTE was designed initially for highvoltage devices, the proposed termination design can also be applied to a lower voltage range. The performance is again benchmarked to the SZ-JTE, SM-JTE, and MFZ-JTE, single implant layouts.
In this section, the n-drift region doping is 3 × 10 15 cm −3 with a thickness, W D of 28 µm. This has a theoretical maximum of 4.02 kV. There are six small trenches in total having 2-µm trench width. The trench space starts at 2 µm and expands by 1 µm per trench. For the 3.3-kV rating, only three floating JTE rings are employed with a pitch of 6 µm, the ring space incrementing from 2 to 4 µm. The total length of the termination for the TSM-JTE is 110 µm (Zone 1 = 70 µm, Zone 2 = 22 µm, and Zone 3 = 18 µm). As mentioned earlier, Zone 1 smooths the electric field around the bottom corner of the big trench and, therefore, it is not possible to reduce Zone 1 proportionally in line with the voltage rating.
The simulated SM-JTE has the same JTE implantation pattern as the TSM-JTE. For the MFZ-JTE, the termination region has been separated into 15 zones with one grounded JTE and 14 floating JTE rings. Their pitch is fixed at 7 µm, the ring spacing starting at 2 µm, increasing with an expansion ratio of 1.08. Unlike at 10 and 20 kV, the MFZ-JTE at 3.3 kV does not have a steep breakdown voltage drop after reaching its maximum breakdown voltage. This occurs because of the approximate equivalence in optimal design lengths (L term ) at 3.3 kV between the JTE and FFR terminations. As the doping in the MFZ-JTE design is increased beyond its optimal value, the rings begin to behave instead like FFRs, maintaining a high V BD . This does not occur in the MFZ-JTE designs at 10 and 20 kV, because the optimal FFR design would occupy a much wider L term than the MFZ-JTE.
Comparing the JTE designs, similar conclusions to those previous voltage ratings can be drawn from the simulation results shown in Fig. 6 and Table III. The proposed TSM-JTE design offers the best tradeoff between maximizing V BD (3.91 kV, 97%) and the process window (±54% at 3 kV). It is also more compact than other JTE designs proposed at a   [13]. However, as mentioned before, in contrast to the higher voltages before, one must also consider FFR designs at 3.3 kV, which can be implanted at the same time as the p+ source contact. A 25-µm drift region in [14] reached 2.8 kV, 80% of the theoretical maximum, in under 50 µm of termination, suggesting that JTE designs at 3.3 kV may not be optimal.

IV. CONCLUSION
The proposed TSM-JTE structure is a novel termination design requiring only one implantation that is appropriate for high-voltage SiC devices. As well as the benefit of requiring only one implant, the TSM-JTE can maximize V BD , requiring only a relatively narrow termination length. Furthermore, its wide implantation dose window means it is practically realizable.
The TSM-JTE has been benchmarked to other singleimplant JTE structures, the SZ-JTE, SM-JTE, and MFZ-JTE, at 10, 20, and 3.3 kV. At 10 kV, the optimal TSM-JTE achieves a peak breakdown voltage of 14 kV (93% of the theoretical maximum) with an implantation window of ±46%. This is achieved with a termination length of just 250 µm, with the SM-JTE and MFZ-JTE design at this length unable to match V BD and implantation window. In comparison with published work, the TSM-JTE termination length is much narrower, 58% and 44% of the SM-JTE [4] and MFZ-JTE [6] designs. Compared with the TSM-JTE, the termination length of the 15-kV trench design in [7] is narrower by 50 µm, but the implantation window is narrower and the fabrication process more complex.
In optimizing the termination structures for 20 kV, the TSM-JTE offers the highest V BD (24.3 kV; 92% of maximum) and a process window of ±32% in a termination length of 500 µm. This compares well with a two-step implanted SM-JTE in the literature [12], which has a 20-kV window of ±35%, a termination length 20% wider, and twice the implantation cost. At 3.3 kV, the TSM-JTE remains the best JTE design, particularly, its dose window, but the chip area reduction is less significant when compared with FFRs.
The introduction of trench structures into the termination region will likely result in interface charge on the trench sidewalls. However, in this article, the impact of interface and oxide charge on the dose window shift has not been studied. In the future, the simulation will be calibrated to account for these effects, using experimental results.