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Simulations and measurements of failure modes in SiC Cascode JFETs under short circuit conditions

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Agbo, Sunday Nereus, Bashar, Erfan, Wu, Ruizhu, Mendy, Simon, Gonzalez, Jose Ortiz and Alatise, Olayiwola M. (2021) Simulations and measurements of failure modes in SiC Cascode JFETs under short circuit conditions. In: 2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL), Cartagena, Colombia, 2-5 Nov 2021. Published in: 2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL) pp. 1-7. ISSN 1093-5142. doi:10.1109/COMPEL52922.2021.9646031

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Official URL: http://dx.doi.org/10.1109/COMPEL52922.2021.9646031

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Abstract

Using experimental measurements and finite element simulations, this paper investigates the failure mode of SiC Cascode JFETs under short circuit (SC) conditions. Unlike SiC MOSFETs, where failure results in a shorted gate-source terminal (resulting from gate oxide failure), in SiC Cascode JFETs, failure usually occurs in drain-source short with the gate of the Low Voltage (LV) silicon MOSFET still operational. Measurements show that after the LV Si MOSFET gate is turned OFF, a high tail current results in the Cascode drain terminal with the drain-source voltage falling to approximately half of the blocking voltage, suggesting that the JFET is in linear mode. Finite element simulations show that thermally generated carriers in the JFET depletion region cause high leakage currents through the internal JFET gate terminal capable of turning-ON the JFET (after turn-OFF of the LV Si MOSFET) into linear mode. The measured short circuit withstand time (SCWT) is shown to be independent of temperature unlike silicon MOSFETs where the SC withstand time increases with the initial temperature.

Item Type: Conference Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
T Technology > TP Chemical technology
Divisions: Faculty of Science > Engineering
Library of Congress Subject Headings (LCSH): Short circuits , Silicon carbide , Field-effect transistors , Industrial electronics , Metal oxide semiconductor field-effect transistors
Journal or Publication Title: 2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL)
Publisher: IEEE
ISSN: 1093-5142
Book Title: 2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL)
Official Date: 23 December 2021
Dates:
DateEvent
23 December 2021Published
24 October 2021Accepted
Page Range: pp. 1-7
DOI: 10.1109/COMPEL52922.2021.9646031
Status: Peer Reviewed
Publication Status: Published
Publisher Statement: © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Access rights to Published version: Restricted or Subscription Access
RIOXX Funder/Project Grant:
Project/Grant IDRIOXX Funder NameFunder ID
EP/R004366/1[EPSRC] Engineering and Physical Sciences Research Councilhttp://dx.doi.org/10.13039/501100000266
Conference Paper Type: Paper
Title of Event: 2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL)
Type of Event: Conference
Location of Event: Cartagena, Colombia
Date(s) of Event: 2-5 Nov 2021

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