Design and VLSI architecture and implementation of wave digital filters using short signed digit coefficients
UNSPECIFIED. (1996) Design and VLSI architecture and implementation of wave digital filters using short signed digit coefficients. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 143 (5). pp. 259-266. ISSN 1350-2409Full text not available from this repository.
The good dynamic range, low round-off noise characteristics and low coefficient sensitivity of wave digital filters make them suitable for realisations with short coefficient word-lengths, The authors discuss the design and VLSI implementation of a wave digital filter architecture using short signed digit coefficient ranges. The fundamental processing block employed in the implementation is the two port adaptor. Restricting the coefficients to this particular form reduces the number of levels of addition required in its implementation. Both the algorithmic and architectural aspects of this are considered. The resultant hardware increases the upper operating frequency, or sample rate, of the realisation, but at the expense of restrictions in the range of filter specifications that can be met. Hardware for a low latency, high clock rate adaptor is developed and cast into a form suited to VLSI implementation. A demonstrator for the concept has been designed and successfully fabricated in 1 mu m standard-cell CMOS technology. It is a programmable, cascadable device that may be applied to all standard filter types. The chip has a die area of 12.7 mm(2) and has been successfully tested to a clock rate of 30 MHz, which is twice the maximum filter sample rate.
|Item Type:||Journal Article|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Journal or Publication Title:||IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS|
|Publisher:||IEE-INST ELEC ENG|
|Official Date:||October 1996|
|Number of Pages:||8|
|Page Range:||pp. 259-266|
Actions (login required)
Downloads per month over past year