Realisation and implementation of a sigma-delta bitstream FIR filter
UNSPECIFIED (1996) Realisation and implementation of a sigma-delta bitstream FIR filter. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 143 (5). pp. 267-273. ISSN 1350-2409Full text not available from this repository.
Sigma-delta signal processing or SDSP has been proposed as a method for reducing system costs by eliminating the decoding of a Sigma Delta bitstream prior to processing. The design problems inherent in this are examined, and the tradeoff to the more conventional approach through the study of a bitstream FIR filter is analysed. It is found that the system imposes particular constraints on the design of the digital Sigma Delta modulator used to remodulate the FIR filter output. Also, the system cost of the SDSP FIR filter is less than that for the decoded PCM filter below a certain number of taps, currently estimated as at least 80. The design of a VLSI demonstrator that implements 16 FIR taps and remodulator, has 16-bit dynamic range and is cascadable for higher filter orders is also presented.
|Item Type:||Journal Article|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|Journal or Publication Title:||IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS|
|Publisher:||IEE-INST ELEC ENG|
|Number of Pages:||7|
|Page Range:||pp. 267-273|
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