UNSPECIFIED (1996) Analysis of convolutional encoders and synthesis of rate-2/n Viterbi decoders. [Journal Item]

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Abstract

In this correspondence, the problem of obtaining efficient hardware for Viterbi decoders fur high-rate convolutional encoders is addressed. It is first shown that the graphs describing the interconnection of the add-compare-select units required may be classified in terms of structures of which there are only a small number for a given code constraint length, They correspond to the assignment of individual register lengths in the ensemble of shift registers in the feedforward encoder, The structures relate to the partitioning or the states such that common successors are grouped together and successive partitioning leads to a hierarchical, modular VLSI layout method, Example symbolic grid layouts are given for 16- and 64-state codes, It is noted that within a given structure, the parity check matrices map into local wiring patterns implying a method for implementing class-universal programmable or adaptive decoders.

Item Type:	Journal Item
Subjects:	Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TK Electrical engineering. Electronics Nuclear engineering
Journal or Publication Title:	IEEE TRANSACTIONS ON INFORMATION THEORY
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
ISSN:	0018-9448
Date:	July 1996
Volume:	42
Number:	4
Number of Pages:	6
Page Range:	pp. 1280-1285
Publication Status:	Published
URI:	http://wrap.warwick.ac.uk/id/eprint/18733

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