UNSPECIFIED (1995) CHARACTERIZATION BASED BOTTLENECK ANALYSIS OF PARALLEL SYSTEMS. SUPERCOMPUTER, 11 (4). pp. 89-101. ISSN 0168-7875

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Abstract

Bottleneck analysis plays an important role in the early design of parallel computers and programs. In this paper a methodology for bottleneck analysis based on an instruction level characterisation technique is presented. The methodology is based on the assumption that a bottleneck is caused by the slowest component of a computing system, These components are: memory (internal, external), processor (CPU, FPU), communication and I/O. Three metrics were used to identify bottlenecks in the system components. These are the B-ratio, the communication-computation ratio and the memory-processing ratio. These ratios are dimensionless and indicate the presence of a bottleneck when their values exceed unity. The methodology is illustrated and validated using a communication intensive linear solver algorithm (Gauss-Jordan elimination) which was implemented on a mesh connected distributed memory parallel computer (128 T800 Parsytec SuperCluster).

Item Type:	Journal Article
Subjects:	Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software
Journal or Publication Title:	SUPERCOMPUTER
Publisher:	ASFRA
ISSN:	0168-7875
Date:	September 1995
Volume:	11
Number:	4
Number of Pages:	13
Page Range:	pp. 89-101
Publication Status:	Published
URI:	http://wrap.warwick.ac.uk/id/eprint/19433

Data sourced from Thomson Reuters' Web of Knowledge

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