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VLSI implementation of a new bit-level pipelined architecture for 2-D allpass digital filters
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UNSPECIFIED (1995) VLSI implementation of a new bit-level pipelined architecture for 2-D allpass digital filters. In: 1995 IEEE International Symposium on Circuits and Systems (ISCAS-1995), APR 30-MAY 03, 1995, SEATTLE, WA.
Full text not available from this repository.| Item Type: | Conference Item (UNSPECIFIED) |
|---|---|
| Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TS Manufactures T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Series Name: | IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS |
| Journal or Publication Title: | 1995 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3 |
| Publisher: | I E E E |
| ISBN: | 0-7803-2570-2 |
| ISSN: | 0277-674X |
| Date: | 1995 |
| Number of Pages: | 4 |
| Page Range: | pp. 724-727 |
| Publication Status: | Published |
| Title of Event: | 1995 IEEE International Symposium on Circuits and Systems (ISCAS-1995) |
| Location of Event: | SEATTLE, WA |
| Date(s) of Event: | APR 30-MAY 03, 1995 |
| URI: | http://wrap.warwick.ac.uk/id/eprint/19684 |
Data sourced from Thomson Reuters' Web of Knowledge
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