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COMPARISON OF 2-PHASE LATCH CONFIGURATIONS FOR PIPELINED PROCESSORS IN MOS VLSI - CASE-STUDY - A CMOS SYSTOLIC MULTIPLIER
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UNSPECIFIED (1990) COMPARISON OF 2-PHASE LATCH CONFIGURATIONS FOR PIPELINED PROCESSORS IN MOS VLSI - CASE-STUDY - A CMOS SYSTOLIC MULTIPLIER. IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 137 (4). pp. 261-265. ISSN 0956-3768
Full text not available from this repository.| Item Type: | Journal Article |
|---|---|
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Journal or Publication Title: | IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS |
| Publisher: | IEE-INST ELEC ENG |
| ISSN: | 0956-3768 |
| Date: | August 1990 |
| Volume: | 137 |
| Number: | 4 |
| Number of Pages: | 5 |
| Page Range: | pp. 261-265 |
| Publication Status: | Published |
| URI: | http://wrap.warwick.ac.uk/id/eprint/23160 |
Data sourced from Thomson Reuters' Web of Knowledge
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