The Library

High-frequency performance of Schottky source/drain silicon pMOS devices

Tools

Raskin, J.-P. (Jean-Pierre), 1971-, Pearman, D. J., Pailloncy, G., Larson, J. M., Snyder, J., Leadley, D. R. (David R.) and Whall, Terry E.. (2008) High-frequency performance of Schottky source/drain silicon pMOS devices. IEEE Electron Device Letters, Vol.29 (No.4). pp. 396-398. ISSN 0741-3106

PDF
WRAP_Leadley_High_Frequency_performance.pdf - Draft Version - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader
Download (142Kb)

Official URL: http://dx.doi.org/10.1109/LED.2008.918250

Abstract

A radio-frequency performance of 85-nm gate-length p-type Schottky barrier (SB) with PtSi source/drain materials is investigated. The impact of silicidation annealing temperature on the high-frequency behavior of SB MOSFETs is analyzed using an extrinsic small-signal equivalent circuit. It is demonstrated that the current drive and the gate transconductance strongly depend on the silicidation anneal temperature, whereas the unity-gain cutoff frequency of the measured devices remains nearly unchanged.

Item Type:	Journal Article
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering Q Science > QC Physics
Divisions:	Faculty of Science > Physics
Library of Congress Subject Headings (LCSH):	Metal oxide semiconductor field-effect transistors -- Research, Metal semiconductor field-effect transistors -- Research, Annealing of metals -- Research, Electric circuits, Equivalent
Journal or Publication Title:	IEEE Electron Device Letters
Publisher:	IEEE
ISSN:	0741-3106
Date:	21 March 2008
Volume:	Vol.29
Number:	No.4
Number of Pages:	3
Page Range:	pp. 396-398
Identification Number:	10.1109/LED.2008.918250
Status:	Peer Reviewed
Access rights to Published version:	Open Access
References:	[1] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain,” Proc. IEEE, vol. 56, no. 8, pp. 1400–1402, Aug. 1968. [2] C. J. Koeneke, S. M. Sze, R. M. Levin, and E. Kinsbron, “Schottky MOSFET for VLSI,” in IEDM Tech. Dig., 1981, pp. 466–469. [3] J. R. Tucker, C. Wang, and P. S. Carney, “Silicon field-effect transistor based on quantum tunneling,” Appl. Phys. Lett., vol. 65, no. 5, pp. 618– 620, Aug. 1994. [4] M. Fritze, C. L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. L. Keast, J. Snyder, and J. Larson, “High-speed Schottky-barrier pMOSFET with fT = 280 GHz,” IEEE Electron Device Lett., vol. 25, no. 4, pp. 220–222, Apr. 2004. [5] J. M. Larson and J. Snyder, “Overview and status of metal S/D Schottkybarrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048–1058, May 2006. [6] “Process integration, devices, and structures,” International Technology Roadmap for Semiconductors, 2003, Austin, TX: Semiconductor Industry Association. [7] D. J. Pearman, G. Pailloncy, J.-P. Raskin, J. M. Larson, and T. E. Whall, “Static and high-frequency behavior and performance of Schottky barrier p-MOSFET devices,” IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2796–2802, Oct. 2007. [8] G. Pailloncy and J.-P. Raskin, “New de-embedding technique based on Cold-FET measurement,” in Proc. 36th EuMW—EuMC, Manchester, U.K., Sep. 10–15, 2006, pp. 460–463. [9] A. Chatterjee, J. Yoon, S. Zhao, S. Tang, K. Sadra, S. Crank, H. Mogul, R. Aggarwal, B. Chatterjee, S. Lytle, C. T. Lin, K. D. Lee, J. Kim, Q. Z. Hong, T. Kim, L. Olsen, M. Quevedo-Lopez, K. Kirmse, G. Zhang, C. Meek, D. Aldrich, H. Mair, M. Mehrotra, L. Adam, D. Mosher, J. Y. Yang, D. Crenshaw, B. Williams, J. Jacobs, M. Jain, J. Rosal, T. Houston, J. Wu, N. S. Nagaraj, D. Scott, S. Ashburn, and A. Tsao, “A 65 nm CMOS technology for mobile and digital signal processing applications,” in IEDM Tech. Dig., 2004, pp. 665–668. [10] S. Thompson, P. Packan, and M. Bohr, “MOS scaling: Transistor challenges for the 21st century,” Intel Technol. J., vol. Q3, pp. 1–19, 1998. [11] D. Connellly, C. Faulkner, and D. E. Grupp, “Optimizing Schottky S/D offset for 25 nm dual-gate CMOS performance,” IEEE Electron Device Lett., vol. 24, no. 6, pp. 411–413, Jun. 2003. [12] R. Rios and N. A. Arora, “Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects,” in IEDM Tech. Dig., 1994, pp. 613–616. [13] J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and J.-P. Colinge, “Accurate SOI MOSFET charaterisation at microwave frequencies for device performance optimisation and analogue modelling,” IEEE Trans. Electron Devices, vol. 45, no. 5, pp. 1017–1025, May 1998. [14] R. Valentin, E. Dubois, J.-P. Raskin, G. Dambrine, G. Larrieu, N. Breil, and F. Danneville, “Investigation of high frequency performances for Schottky-barrier p-MOSFET,” in Proc. 7th Topical Meeting Silicon Monolithic Integr. Circuits RF Syst.—SiRF, Long Beach, CA, Jan. 10–12, 2007, pp. 32–35. [15] Z. Xia, G. Du, X. Liu, J. Kang, and R. Han, “Investigation of RF performance of nano-scale ultra-thin-body Schottky-barrier MOSFETs using Monte Carlo simulation,” in Proc. IEEE Conf. Electron Devices Solid- State Circuits, Dec. 19–21, 2005, pp. 305–308. [16] J.-P. Raskin, T. M. Chung, V. Kilchytska, D. Lederer, and D. Flandre, “Analog/RF performance of multiple-gate SOI devices: Wideband simulations and characterization,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1088–1094, May 2006.
URI:	http://wrap.warwick.ac.uk/id/eprint/2983