The Library

Performance enhancements in scaled strained-SiGe pMOSFETs with HfSiOx/TiSiN gate stacks

Tools

Alatise, Olayiwola M., Olsen, Sarah H., Cowern, Nicholas E. B., O'Neill, Anthony G. and Majhi, Prashant. (2009) Performance enhancements in scaled strained-SiGe pMOSFETs with HfSiOx/TiSiN gate stacks. IEEE Transactions on Electron Devices, Vol.56 (No.10). pp. 2277-2284. ISSN 0018-9383

Preview

PDF
WRAP_Alatise_1070562-es-091211-ieee_ted_performance_enhancements_strained_sige_pmosfets.pdf - Accepted Version - Requires a PDF viewer.
Download (479Kb)

Official URL: http://dx.doi.org/10.1109/TED.2009.2028375

Abstract

The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.

Item Type:

Journal Article

Subjects:

Q Science > QC Physics
T Technology > TK Electrical engineering. Electronics Nuclear engineering

Divisions:

Faculty of Science > Engineering

Library of Congress Subject Headings (LCSH):

Electron mobility, Silicon alloys, Metal oxide semiconductors, Complementary, Metal oxide semiconductor field-effect transistors

Journal or Publication Title:

IEEE Transactions on Electron Devices

Publisher:

IEEE

ISSN:

0018-9383

Official Date:

2009

Dates:

Date	Event
2009	Published

Volume:

Vol.56

Number:

No.10

Number of Pages:

Page Range:

pp. 2277-2284

Identifier:

10.1109/TED.2009.2028375

Status:

Peer Reviewed

Publication Status:

Published

Access rights to Published version:

Restricted or Subscription Access

Funder:

Engineering and Physical Sciences Research Council (EPSRC), SEMATECH (Organization)

References:

[1] S. H. Olsen, A. G. O'Neill, S. Chattopadhyay, L. S. Driscoll, K. S. K. Kwa, D. Norris, A. Cullis, and D. J.
Paul, "Study of single and dual channel designs of high performance strained Si/SiGe n-MOSFETs,"
IEEE Trans. Electron Devices, vol. 51, pp. 1245-1253, 2004.
[2] V. Kesan, S. Subbanna, P. Restle, M. Tejwani, J. Altken, S. Lyer, and J. Ott, "High performance 0.25 um
pMOSFETs with Silicon-Germanium channels for 300K and 77K operation," in IEDM Tech. Dig., pp.
25-28, 1991.
[3] N. Collaert, P. Verheyen, K. Meyer, R. Loo, and M. Caymax, "High performance Si/SiGe pMOSFETs
fabricated in a standard CMOS process technology," Solid State Electron., vol. 47, pp. 1173-1177, 2003.
[4] A. Lindgren, P. Hellberg, M. Haartman, D. Wu, C. Menon, S. Zhang, and M. Ostling, "Enhanced
intrinsic gain of pMOSFETs with SiGe channel," in Proc. ESSDERC, pp. 175-178, 2002.
[5] R. Loo, N. Collaert, P. Verheyen, M. Caymax, R. Delhougne, and K. Meyer, "Fabrication of 50 nm high
performance strained SiGe pMOSFETs with selective epitaxial growth," Appl. Surf. Sci., vol. 224, pp.
292-296, 2004.
[6] S. Maikap, J. Lee, D. Yim, R. Mahapatra, S. Ray, J. Song, Y. No, and W. Choi, "Physical and electrical
properties of ultrathin HfO2/HfSixOy stacked gate dielectrics on compressively strained Si0.74Ge0.26/Si
heterolayers," J. Vac. Sci. Technol. B, vol. 22, pp. 52-56, 2003.
[7] C. Maiti, S. Maikap, S. Chatterjee, S. Nandi, and S. Samanta, "Hafnium oxide gate dielectric for Si1-
xGex," Solid State Electron., vol. 47, pp. 1995-2000, 2003.
[8] Z. Shi, D. Onsongo, K. Onishi, J. Lee, and S. Banerjee, "Mobility enhancement in surface channel SiGe
PMOSFETs With HfO2 gate dielectrics," IEEE Electron Device Lett., vol. 24, pp. 34-36, January 2003
2003.
[9] Z. Shi, D. Onsongo, and S. Banerjee, "Mobility and performance enhancement on compressively
strained SiGe channel pMOSFETs," Appl. Surf. Sci, vol. 224, pp. 248-253, 2004.
[10] O. Weber, F. Ducroquet, T. Ernst, F. Andrieu, J. Damlencourt, J. Hartmann, B. Guillamourt, A. Papon, H.
Danas, L. Brevard, A. Toffoli, P. Besson, F. Martin, Y. Morand, and S. Delonibus, "55 nm high mobility
SiGe(:C) with HfO2 gate dielectric and TiN metal gate for advanced CMOS," in symp. on VLSI Tech.
Dig., pp. 42-43, 2004.
[11] O. Weber, J. Damlencourt, F. Andrieu, and F. Ducroquet, "Fabrication and mobility characterisitics of
SiGe surface channel pMOSFETs with HfO2/TiN gate stack," IEEE Trans. Electron Devices, vol. 53, pp.
449-456, March 2006 2006.
[12] D. Wu, S. Person, A. Lindgren, G. Sjoblom, P. Hellstrom, J. Olsson, S. Zhang, M. Ostling, E. Ahlgren,
W. Li, and M. Touminen, "ALD Metal Gate/High K Gate Stack for Si and SiGe Surface Channel PMOSFETs."
[13] D. Wu, J. Lu, H. Radamson, P. Hellstrom, Q. Zhang, M. Ostling, E. Ahlgren, E. Tois, and M. Tuominen,
"Influence of surface treatment prior to ALD high k dielectrics on the performance of SiGe surface
channel pMOSFETs," IEEE Electron Device Lett., vol. 25, pp. 289-291, May 2004 2004.
[14] H Harris, P Kalra, P Majhi, M Hussain, D Kelly, J Oh, D He, C Smith, J Barnett, P Kirsch, G Gebara, J
Jur, T Ma, G Sung, S Thompson, B Lee, H Tseng, and R. Jammy, "Band engineered low PMOS Vt with
high-k/metal gate featured in a dual channel CMOS integration scheme," in symp. on VLSI Tech. Dig.,
pp. 154-155, 2007.
[15] O. Sullivan, V. Kaushik, J. Everaert, L. Trojan, L. Ragnarsson, L. Pantisano, E. Rohr, S. DeGendt, and
M. Heyns, "Effectiveness of Nitridation of Hafnium Silicate Dielectrics: A Comparison Between
Thermal and Plasma Nitridation," IEEE Trans. Electron Devices, vol. 54, pp. 1771-1775, 2007.
[16] G. Nicholas, D. Brunco, A. Dimoulas, J. Steenbergen, F. Bellenger, M. Houssa, M. Caymax, M. Meuris,
Y. Panayiotatos, and A. Sotiropoulus, "Germanium MOSFETs with CeO2/HfO2/TiN gate stacks," IEEE
Trans. Electron Devices, vol. 54, pp. 1425-1430, June 2007 2007.
[17] N. Wu, Q. Zhang, N. Balasubramanian, D. Chan, and C. Zhu, "Characterisitics of Self Aligned Gate
First Ge p and n Channel MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation,"
IEEE Transactions on Electron Devices, vol. 54, pp. 733-741, April 2007 2007.
[18] K. Onishi, C. Kang, R. Choi, H. Cho, and S. Gopalan, "Improvement of surface carrier Mobility of
HfO2 MOSFETs by high temperature forming gas annealing," IEEE Trans. Electron Devices, vol. 50,
pp. 384-390, February 2003 2003.
[19] D. Schroeder, "Semiconductor material and device characterization," Wiley, 1998.
[20] G. Dalapati, S. Chattopadhyay, K. Kwa, S. Olsen, Y. Tsang, R. Agaiby, A. O'Neill, P. Dobrosz, and S.
Bull, "Impact of strained Si thickness and Ge out-diffusion on gate oxide quality for strained Si surface
channel n-MOSFETs," IEEE Trans. Electron Devices, vol. 53, pp. 1142-1152, 2006.
[21] K. Kwa, S. Chattopadhyay, S. Olsen, A. O'Neill, L. Driscoll, and A. O'Neill, "Optimisation of channel thickness in Strained Si/SiGe MOSFETs," in Proc. ESSDERC, 2003.
[22] M. Hartman, G. Malm, and M. Ostling, "Comprehensive Study of Low Frequency Noise and Mobility
in Si and SiGe pMOSFETs with High-k Gate Dielectrics and TiN Gate," Trans Electron Dev, vol. 53, pp.
836-843, 2006.
[23] S. Datta, J. Brask, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, M. Metz, A. Majumdar, M.
Radosavljevic, and R. Chau, "Advanced Si and SiGe strained channel NMOS and PMOS transistors
with high k/metal gate stack," IEEE BCTM, vol. 194-197, 2004.
[24] B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, P. Masson, T. Tuche, A. Papn, J. Damlencourt,
S. Maitrejean, M. Rivoire, C. Leroux, S. Christoloveanu, G. Ghibaudo, J. Autran, T. Stotnicki, and S.
Deleonibus, "75 nm damascene metal gate and high k integration for advanced CMOS devices," in
IEDM Tech. Dig., 2002.
[25] F. Lime, K. Oshima, M. Casse, G. Ghibaudo, S. Christoloveanu, B. Guillamourt, and H. Iwai, "Carrier
mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric," Solid State Electron.,
vol. 47, pp. 1617-1621, 2003.
[26] K. Rajendran and W. Schoenmaker, "Studies of boron diffusivity in strained SiGe epitaxial layers," J.
Appl. Phys., vol. 89, pp. 980-987, 2001.
[27] N Zangenberg, J Pedersen, J Hansen, and N. Larsen, "Boron and phosphorus diffusion in strained and
relaxed Si and SiGe," J. Appl. Phys., vol. 94, pp. 3883-3890, 15 September 2003 2003.
[28] N Cowern, P Zalm, P Van der Sluis, D Gravesteijn, and W. Boer, "Diffusion in strained Si(Ge)," Phys.
Rev. Lett., vol. 72, pp. 2585-2588, 30 November 1994 1994.
[29] Y. Taur, "MOSFET channel length: extraction and interpretation," IEEE Trans. Electron Devices, vol.
47, pp. 160-169, 2000.
[30] J Huang, Z Liu, M Jeng, P Ko, and C. Hu, "A physical model for MOSFET output resistance," in IEDM
Tech. Dig., pp. 569-572, 1992.
[31] J Liu and M. Ozturk, "Nickel germanosilicide contacts formed on heavily boron doped SiGe
sourcedrain junctions for nanoscale CMOS," IEEE Trans. Electr. Devices, vol. 52, pp. 1535-1540, 2005.
[32] K Pey, W Choi, S Chattopadhyay, H Zhao, F Fitzgerald, and D. Antoniadis, "Thermal reaction of nickel
and SiGe alloy," J. Vac. Sci. Technol, vol. 20, pp. 1903-1910, 2002.
[33] A Saha, S Chattopadhyay, and C. Maiti, "Contact metallization on strained Si," Solid State Electron.,
vol. 48, pp. 1391-1399, 2004.
[34] S. Zhang, "Nickel based contact metallization for SiGe MOSFETs: progress and challenges,"
Microelectronic Engineering, vol. 70, pp. 174-185, 2003.
[35] J. Shim, H. Oh, H. Choi, T. Sakaguchi, H. Kurino, and M. Koyanagi, "SiGe elevated source/drain
structure and nickel contact layer for 0.1 um MOSFET fabrication," Appl. Surf. Sci, vol. 224, pp. pp
260-264, 2004.
[36] K. Lim and X. Zhou, "A Physically Based Semi-Empirical Series Resistance Model for Deep-
Submicron MOSFET I-V Modelling," IEEE Trans. Electron Devices, vol. 47, pp. 1300-1302, 2000.
[37] R. Langevelde and F. Klaassen, "Effect of gate field dependent mobility degradation on distortion
analysis in MOSFETs," IEEE Trans. Electron Devices, vol. 44, pp. 2044-2052, 1997.
[38] K. Rim, J. Hoyt, and J. Gibbons, "Analysis and fabrication deep submicron strained Si n-MOSFETs,"
IEEE Trans. Electron Devices, vol. 47, pp. 1406-1415, 2000.
[39] K. Ikeda, Y. Yamashitta, A. Endoh, T. Fukano, K. Hikosaka, and T. Mimura, "50 nm gate schottky
source/drain pMOSFETs with a SiGe channel," IEEE Electron Device Lett., vol. 23, pp. 670-672, 2002.
[40] J. Dismukes, L. Ekstrom, E. Steigmeier, I. Kudman, and D. Beers, "Thermal and electrical properties of
heavily doped Ge-Si alloys up to 1300 K," J. Appl. Phys., vol. 35, pp. 2899-2907, 1964.
[41] R. Agaiby, Y. Yang, S. H. Olsen, A. G. O'Neill, G. Eneman, P. Verheyen, R. Loo, and C. Claeys,
"Quantifying Self-Heating Effects with Scaling in Globally Strained Si MOSFETs," Solid-State
Electron., vol. 51, pp. 1473-1478, 2007/0 2007.
[42] W Jin, W Liu, S Fung, P Chan, and C. Hu, "SOI thermal impedance extraction methodology and its
significance for circuit simulation," IEEE Trans. Electron Devices, vol. 48, pp. 730-736, 2001.