The Library

Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

Tools

Alatise, Olayiwola M., Olsen, Sarah H. and O'Neill, Anthony G.. (2010) Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics. Solid-State Electronics, Vol.54 (No.6). pp. 628-634. ISSN 00381101

Preview

PDF
WRAP_Alatise_1070562-es-091211-solid_state_electronics_strained_si_mosfet_linearity.pdf - Accepted Version - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader
Download (942Kb)

Official URL: http://dx.doi.org/10.1016/j.sse.2009.12.036

Abstract

As gate dielectrics are scaled to a few atomic layers and the channel doping is increased to mitigate short channel effects, high vertical electric fields cause considerable mobility degradation through surface-roughness scattering in silicon MOSFETs. This high-field mobility degradation is known to influence the harmonic distortion through higher order derivatives of the drain current. Failure to take these higher order derivatives into account can cause significant error in the predictive evaluation of linearity (VIP3) in MOSFETs. Electrical measurements are used to extract the 2nd order mobility degradation factor (θ2) from strained silicon MOSFETs fabricated on silicon germanium strain relaxed buffers with 15%, 20% and 25% germanium. Linearity and high-field mobility degradation are shown to be independent of strain in spite of atomic force microscopy measurements showing that the amplitude of the root-mean-square surface roughness increases with the germanium content. It is also shown that θ2 is required for accurate modelling of linearity. The impact of oxide thickness on linearity is also investigated through θ2. In this paper, an analytical relationship between θ2 and the effective oxide thickness is developed and validated by electrical measurements on MOSFETs with different oxide thicknesses and θ2 values from the literature. Using the extracted θ2 values as inputs to analytical MOSFET models, a correlation between the oxide thickness and linearity is analyzed.

Item Type:

Journal Article

Subjects:

Q Science > QC Physics
T Technology > TK Electrical engineering. Electronics Nuclear engineering

Divisions:

Faculty of Science > Engineering

Library of Congress Subject Headings (LCSH):

Electron mobility, Silicon, Silicon alloys, Metal oxide semiconductors, Complementary, Metal oxide semiconductor field-effect transistors

Journal or Publication Title:

Solid-State Electronics

Publisher:

Pergamon

ISSN:

00381101

Official Date:

2010

Dates:

Date	Event
2010	Published

Volume:

Vol.54

Number:

No.6

Page Range:

pp. 628-634

Identification Number:

10.1016/j.sse.2009.12.036

Status:

Peer Reviewed

Publication Status:

Published

Access rights to Published version:

Restricted or Subscription Access

Funder:

Engineering and Physical Sciences Research Council (EPSRC), Seventh Framework Programme (European Commission) (FP7)

References:

[1] Woerlee, "RF CMOS performance trends," IEEE Trans. Electron Devices,
vol. 48, pp. 1776-1782, 2001.
[2] Murmann, "Impact of scaling on analog performance and associated
modelling needs," IEEE Trans. Electron Devices, vol. 53, 2006.
[3] K. Rim, J. Hoyt, and J. Gibbons, "Analysis and fabrication deep submicron
strained Si n-MOSFETs," IEEE Trans. Electron Devices, vol. 47, pp. 1406-
1415, 2000.
[4] S. Kang, B. Choi, and B. Kim, "Linearity analysis of CMOS for RF
application," IEEE Transactions on Microwave Theory and Techniques, vol.
51, pp. 972-978, 2003.
[5] R. Langevelde, L. Tiemeijer, M. Knitel, R. Roes, Woerlee, and D. Klaassen,
"RF distortion in deep submicron CMOS technologies," in IEDM Tech. Dig.,
pp. 807-810, 2000.
[6] C. Choi, Z. Yu, and R. Dutton, "Impact of poly gate depletion on MOS RF
linearity," IEEE Electron Device Lett, vol. 24, pp. 330-332, 2003.
[7] R. Langevelde and F. Klaassen, "Effect of gate field dependent mobility
degradation on distortion analysis in MOSFETs," IEEE Trans. Electron
Devices, vol. 44, pp. 2044-2052, 1997.
[8] B. Toole, C. Plett, and M. Cloutier, "RF circuit implications of moderate
inversion enhanced linear region in MOSFETs," IEEE Trans. Circ. Systems,
vol. 51, pp. 319-328, 2004.
[9] B. Toole and M. Cloutier, "RF circuit implications of a low current linearity
"sweet spot" in MOSFETs," ESSCIRC, pp. 619-622, 2002.
[10] X. Xi, K. Cao, X. Jin, H. Wan, M. Chan, and C. Hu, "Distortion simulation of
90nm nMOSFET for RF application," IEEE, pp. 247-250, 2001.
[11] W. Ma and S. Kaya, "Impact of device physics on DG and SOI MOSFET
linearity," Solid State Electron., vol. 48, pp. 1741-1746, 2004.
[12] P. McLarty, S. Cristoloveanu, O. Faynot, V. Misra, J. Hauser, and J. Wortman,
"A simple parameter extraction method for ultra-thin oxide MOSFETs," Solid
State Electron., vol. 38, pp. 1175-1177, 1995.
[13] K. yu, "Mobility Degradation due to the Gate Field in the Inversion Layer of
MOSFETs," IEEE Electron Device Lett., vol. 3, pp. 292-293, 1982.
[14] G. Ghibaudo, "A New Method for the Extraction of MOSFET Parameters,"
IEEE Electronic Letters, vol. 24, pp. 543-545, 1988.
[15] G. Kar, S. Maikap, S. Banerjee, and S. Ray, "Series resistance and mobility
degradation factor in C-incorporated SiGe heterostructure p-type metal oxide
semiconductor field effect transistors," Semicond. Sci. Tech, vol. 17, pp. 938-
941, 2002.
[16] T. Ernst, S. Christoloveanu, G. Ghibaudi, T. Oussie, S. Horiguchi, Y. Ono, Y.
Takahashi, and K. Murase, "Ultimately Thin Double-Gate SOI MOSFETs,"
IEEE Trans. Electron Devices, vol. 50, pp. 830-838, 2003.
[17] F. Lime, C. Guiducci, R. Clerc, G. Ghibaudo, C. Leroux, and T. ernst,
"Characterization of effective mobility by split (CV) technique in NMOSFETs
with ultra-thin gate oxides," Solid State Electron., vol. 47, pp. 1147-1153,
2003.
[18] F. Lime, K. Oshima, M. Casse, G. Ghibaudo, S. Christoloveanu, B.
Guillamourt, and H. Iwai, "Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric," Solid State Electron., vol. 47, pp. 1617-
1621, 2003.
[19] S. Olsen, A. O'Neill, D. Norris, A. Cullis, N. Woods, J. Zhang, K. Fobelets,
and K. H, "Strained Si/SiGe n-channel MOSFETs: impact of cross-hatching
on device performance," Semicond. Sci. Technol., vol. 17, pp. 655-661, 2002.
[20] Currie, "Carrier mobilities and process stabilities in strained n and p-
MOSFETs fabricated on SiGe virtual substrates," J. Vac. Sci. Technol., vol.
19, 2001.
[21] D. Schroeder, "Semiconductor material and device characterization," Wiley,
1998.
[22] J. Watling, L. Yang, M. Borici, R. Wilkins, A. Asenov, J. Barker, and S. Roy,
"The impact of interface roughness scattering and degenracy in relaxed and
strained Si n MOSFETs," Solid State Electron., vol. 48, pp. 1337-1346, 2004.
[23] M. Fischetti, F. Gamiz, and W. Hansch, "On the enhanced mobility in strained
silicon inversion layers," J. Appl. Phys., vol. 92, pp. 7320-7324, 2002.
[24] Y. Tsividis, "Operation and modelling of the MOS Transistor," 1999.
[25] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of
inversion layer mobility in Si MOSFETs: Part II- Effects of surface
orientation," IEEE Trans. Electron Devices, vol. 41, pp. 2363-2368, 1994.
[26] G. Mazzoni, A. Lacaita, L. Perron, and A. Pirovano, "On surface roughness
limited mobility in highly doped nMOSFETs," IEEE Trans. Electron Devices,
vol. 46, pp. 1423-1428, 1999.
[27] T. Yamanaka, S. Fang, H. Lin, J. Snyder, and C. Helms, "Correlation between
inversion layer mobility and surface roughness measured by AFM," IEEE
Electron Device Lett., vol. 17, pp. 178-180, 1996.
[28] A. Pirovano, A. Lacaita, G. Ghidini, and G. Tallarida, "On the correlation
between surface roughness and inversion layer mobility in Si nMOSFETs,"
IEEE Electron Device Lett., vol. 21, pp. 34-36, 2000.
[29] C. Yue, M. Agostinelli, G. Yeric, and A. Tasch, "Improved universal
MOSFET electron mobility degradation models for circuit simulations," IEEE
Trans. Comp. Aided design of integrated circuits and systems, vol. 12, pp.
1542-1546, 1993.