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Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks

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Alatise, Olayiwola M., Olsen, Sarah H., O'Neill, Anthony G. and Majhi, Prashant. (2010) Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks. Microelectronic Engineering, Vol.87 (No.11). pp. 2196-2199. ISSN 0167-9317

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Abstract

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiOx/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiOx/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.

Item Type: Journal Article
Subjects: Q Science > QC Physics
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Science > Engineering
Library of Congress Subject Headings (LCSH): Metal oxide semiconductor field-effect transistors, Silicon alloys
Journal or Publication Title: Microelectronic Engineering
Publisher: Elsevier BV
ISSN: 0167-9317
Official Date: 2010
Volume: Vol.87
Number: No.11
Number of Pages: 4
Page Range: pp. 2196-2199
Identification Number: 10.1016/j.mee.2010.02.002
Status: Peer Reviewed
Publication Status: Published
Access rights to Published version: Restricted or Subscription Access
References:

[1] P. Majhi, P. Kalra, R. Harris, K. Choi, D. Heh, J. Oh, D. Kelly, R. Choi, B. Cho, S. Banerjee, W. Tsai, H.
Tseng, and R. Jammy, "Demonstration of high performance PMOSFETs Using Si-SiGe-Si quantum
wells with high-k/metal gate stacks," IEEE Electron Device Lett., vol. 29, pp. 99-101, 2008.
[2] Z. Shi, D. Onsongo, K. Onishi, J. Lee, and S. Banerjee, "Mobility enhancement in surface channel SiGe
PMOSFETs With HfO2 gate dielectrics," IEEE Electron Device Lett., vol. 24, pp. 34-36, 2003.
[3] O. Weber, J. Damlencourt, F. Andrieu, and F. Ducroquet, "Fabrication and mobility characterisitics of
SiGe surface channel pMOSFETs with HfO2/TiN gate stack," IEEE Trans. Electron Devices, vol. 53, pp.
449-456, 2006.
[4] H Harris, P Kalra, P Majhi, M Hussain, D Kelly, J Oh, D He, C Smith, J Barnett, P Kirsch, G Gebara, J
Jur, T Ma, G Sung, S Thompson, B Lee, H Tseng, and R. Jammy, "Band engineered low PMOS Vt with
high-k/metal gate featured in a dual channel CMOS integration scheme," in symp. on VLSI Tech. Dig.,
pp. 154-155, 2007.
[5] A. Lindgren, P. Hellberg, M. Haartman, D. Wu, C. Menon, S. Zhang, and M. Ostling, "Enhanced
intrinsic gain of pMOSFETs with SiGe channel," in Proc. ESSDERC, pp. 175-178, 2002.
[6] ITRS, "Radio Frequency and Analog/Mixed Signal Technologies for Wireless Communications," ITRS,
pp. 7-10, 2003.
[7] O. M. Alatise, S. H. Olsen, N. E. B. Cowern, A. G. O'Neill, and P. Majhi, "Performance Enhancements
in Scaled Strained SiGe pMOSFETs with HfSiOX/TiSiN Gate Stacks," IEEE Trans. Electron Devices,
vol. (in print), 2009.
[8] J Huang, Z Liu, M Jeng, P Ko, and C. Hu, "A physical model for MOSFET output resistance," in IEDM
Tech. Dig., pp. 569-572, 1992.
[9] S. Yu, J. Jung, J. Hoyt, and D. Antoniadis, "Strained Si Strained SiGe Dual Channel Layer Structure as
CMOS Substrate for Single Workfunction Metal Technology," IEEE Electron Device Letters, vol. 25,
pp. 402-404, 2004.
[10] M. Temple, D. Paul, Y. Tang, A. Waite, C. Cerrina, A. Evans, X. Li, J. Zhang, S. Olsen, and A. O. Neill,
"Compressively Strained buried channel SiGe pMOSFETs," IEEE Trans. Elect. Devices, 2004.
[11] M. Shima, T. Ueno, T. Kumise, H. Shido, Y. Sakuma, and S. Nakamura, "<100> Channel Strained SiGe
pMOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance," Symposium on VLSI
Technology Digest of Technical Papers, pp. 94-95, 2002.
[12] O. Mironov, M. Myronov, M. Durov, S. Leadley, D. Hackbarth, T. Hock, H. Herzog, U. Konig, H.
Kanel, E. Parker, and T. Whall, "P-Si0.3Ge0.7 and p-Si0.2Ge0.8 MOSFETs of enhanced performance," In
Proc. ESSDERC, pp. 557-560, 2003.
[13] S. Suthram, P. Majhi, G. Sun, P. Kalra, H. Harris, K. Choi, D. Heh, D. Oh, D. Kelly, R. Choi, B. Cho, M.
Hussain, C. Smith, S. Banerjee, W. Tsai, S. Thompson, H. Tseng, and R. Jammy, "High Performance
pMOSFETs using Si/Si1-xGex/Si Quantum Wells with High-k/Metal Gate Stacks and Additive Uniaxial
Strain for 22 nm Technology Node," In IEDM Tech. Dig., pp. 727-730, 2007.
[14] T. Tezuka, N. Sugiyama, T. Mizuno, and S. Takagi, "Ultrathin body SiGe on insulator pMOSFETs with
high mobility SiGe surface channels," IEEE Trans. Electron Devices, vol. 50, pp. 1328-1333, 2003.
[15] J. Colinge, "Fully depleted SOI CMOS for analog applications," IEEE Trans. Electron Devices, vol. 45,
pp. 1010-1016, 1998.
[16] Y Taur, D Zicherman, D Lombardi, P restle, C Hsu, H Hanafi, M Wordeman, B Davari, and G. Shahidi,
"A new "Shift and Ratio" method for MOSFET channel length extraction," IEEE Electron Device Lett.,
vol. 13, pp. 267-269, 1992.
[17] N Zangenberg, J Pedersen, J Hansen, and N. Larsen, "Boron and phosphorus diffusion in strained and
relaxed Si and SiGe," J. Appl. Phys., vol. 94, pp. 3883-3890, 2003.
[18] N Moriya, L Feldman, H Luftman, C King, J Bevk, and B. Freer, "Boron Diffusion in Strained SiGe
Epitaxial Layers," Physical Review Letters, vol. 71, pp. 883-886, 1993.
[19] N Cowern, P Zalm, P Van der Sluis, D Gravesteijn, and W. Boer, "Diffusion in strained Si(Ge)," Phys.
Rev. Lett., vol. 72, pp. 2585-2588, 1994.
[20] Y. Taur, "MOSFET channel length: extraction and interpretation," IEEE Trans. Electron Devices, vol.
47, pp. 160-169, 2000.
URI: http://wrap.warwick.ac.uk/id/eprint/37112

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