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The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs
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Alatise, Olayiwola M., Kwa, Kelvin S. K., Olsen, Sarah H. and O'Neill, Anthony G.. (2010) The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs. Solid-State Electronics, Vol.54 (No.3). pp. 327-335. ISSN 0038-1101
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WRAP_Alatise_1070562-es-091211-solid_state_electronics_self_heating_strained_si_mosfets.pdf - Accepted Version - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader Download (638Kb) |
Official URL: http://dx.doi.org/10.1016/j.sse.2009.09.029
Abstract
The impact of the thickness of the silicon–germanium strain-relaxed buffer (SiGe SRB) on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self-heating at high power levels leads to negative self-gain which can cause anomalous circuit behavior like non-linear phase shifts. Using AC and DC measurements, it is shown that reducing the SRB thickness improves the analog design space and performance by minimizing self-heating. The range of terminal voltages that leverage positive self-gain in 0.1 μm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by over 100% compared with strained Si devices fabricated on conventional SiGe SRBs 4 μm thick. Strained Si nMOSFETs fabricated on thin SiGe SRBs also show 45% improvement in the self-gain compared with the Si control as well as 25% enhancement in the on-state performance compared with the strained Si nMOSFETs on the 4 μm SiGe SRB. The extracted thermal resistance is 50% lower in the strained Si device on the thin SiGe SRB corresponding to a 30% reduction in the temperature rise compared with the device fabricated on the 4 μm SiGe SRB. Comparisons between the maximum drain voltages for positive self-gain in the strained Si devices and the ITRS projections of supply-voltage scaling show that reducing the thickness of the SiGe SRB would be necessary for future technology nodes.
| Item Type: | Journal Article |
|---|---|
| Subjects: | Q Science > QC Physics T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Faculty of Science > Engineering |
| Library of Congress Subject Headings (LCSH): | Metal oxide semiconductor field-effect transistors, Silicon alloys, Silicon, Electron mobility |
| Journal or Publication Title: | Solid-State Electronics |
| Publisher: | Pergamon |
| ISSN: | 0038-1101 |
| Date: | 2010 |
| Volume: | Vol.54 |
| Number: | No.3 |
| Page Range: | pp. 327-335 |
| Identification Number: | 10.1016/j.sse.2009.09.029 |
| Status: | Peer Reviewed |
| Publication Status: | Published |
| Access rights to Published version: | Restricted or Subscription Access |
| Funder: | Seventh Framework Programme (European Commission) (FP7/2007-2013), Sixth Framework Programme (European Commission) (FP6), Engineering and Physical Sciences Research Council (EPSRC) |
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| URI: | http://wrap.warwick.ac.uk/id/eprint/37114 |
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