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Understanding linear-mode robustness in low-voltage trench power MOSFETs
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Alatise, Olayiwola M., Kennedy, Ian, Petkos, George, Khan, Khalid, Dr., Koh, Adrian and Rutter, Philip. (2010) Understanding linear-mode robustness in low-voltage trench power MOSFETs. IEEE Transactions on Device and Materials Reliability, Vol.10 (No.1). pp. 123-129. ISSN 1530-4388
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Official URL: http://dx.doi.org/10.1109/TDMR.2009.2036001
Abstract
The high-temperature electrothermal stability and linear-mode robustness of low-voltage discrete power trench MOSFETs are assessed. The linear-mode robustness is shown to be dependent on the positive temperature coefficient of the subthreshold diffusion current and the MOSFET gain factor. The datasheet threshold voltage temperature coefficient (V GSTX TC) of a power MOSFET is important because it correlates with the linear-mode robustness and the zero-temperature-coefficient (ZTC) point of the device. The impact of the MOSFET active area and the cell pitch on the V GSTX TC is experimentally assessed on fabricated devices. It is shown that the magnitude of the V GSTX TC increases as the MOSFET active area increases, whereas it reduces as the cell pitch increases. The drain voltage at the onset of thermal runaway is shown to increase as the V GSTX TC reduces for the same active area, thereby making the V GSTX TC an indicator of linear-mode robustness. Although the gate voltage at the ZTC point and the magnitude of the V GSTX TC increase with the MOSFET active area, the reduced thermal resistance improves the linear-mode robustness. The implication is that improved device performance in terms of lower specific on-state resistance ( R SPEC in ohm-square millimeter) is at the expense of linear-mode robustness of the power MOSFET since lower R SPEC devices have higher gain factors and higher currents are delivered at weaker inversion levels (and therefore contain higher proportions of subthreshold diffusion currents). In designing power MOSFETs, these parameters must be taken into consideration so as to minimize high-temperature instability and improve linear-mode robustness.
| Item Type: | Journal Article |
|---|---|
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Faculty of Science > Engineering |
| Library of Congress Subject Headings (LCSH): | Metal oxide semiconductor field-effect transistors |
| Journal or Publication Title: | IEEE Transactions on Device and Materials Reliability |
| Publisher: | IEEE |
| ISSN: | 1530-4388 |
| Date: | 2010 |
| Volume: | Vol.10 |
| Number: | No.1 |
| Page Range: | pp. 123-129 |
| Identification Number: | 10.1109/TDMR.2009.2036001 |
| Status: | Peer Reviewed |
| Publication Status: | Published |
| Access rights to Published version: | Restricted or Subscription Access |
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| URI: | http://wrap.warwick.ac.uk/id/eprint/37116 |
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