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Modeling the impact of the trench depth on the gate-drain capacitance in power MOSFETs

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Alatise, Olayiwola M., Parker-Allotey, Nii-Adotei, Jennings, Michael R., Mawby, P. A. (Philip A.), Kennedy, Ian and Petkos, George. (2011) Modeling the impact of the trench depth on the gate-drain capacitance in power MOSFETs. IEEE Electron Device Letters, Vol.32 (No.9). pp. 1269-1271. ISSN 0741-3106

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Official URL: http://dx.doi.org/10.1109/LED.2011.2159476

Abstract

Trench depth is important in low-voltage trench MOSFETs because it affects the switching losses through the gate-drain capacitance (C(GD)). The dependence of C(GD) on the trench depth is investigated by analytical modeling and experimental characterization. An analytical model that relates the trench depth, trench bottom oxide thickness, n(-) layer doping, and drain voltage (V(D)) to C(GD) is developed and validated by experimental measurements. Trench MOSFETs with thick bottom oxides have been fabricated with 1.3-, 1.5-, 1.7-, and 2-mu m deep trenches. CV measurements show that C(GD) is proportional to the trench depth at low V(D) and becomes increasingly independent of trench depth as V(D) is increased. The model is used to show that this is due to C(GD) being dominated by the oxide capacitance at low V(D) and the depletion capacitance at high V(D). The fact that the average thickness of the trench bottom oxide decreases as the trench depth increases (because of additional sidewall oxide overlapping the drain) means that the impact of the trench depth is the highest at low V(D), where the depletion capacitance is ineffective.

Item Type:	Journal Article
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:	Faculty of Science > Engineering
Library of Congress Subject Headings (LCSH):	Metal oxide semiconductor field-effect transistors -- Mathematical models
Journal or Publication Title:	IEEE Electron Device Letters
Publisher:	IEEE
ISSN:	0741-3106
Date:	September 2011
Volume:	Vol.32
Number:	No.9
Number of Pages:	3
Page Range:	pp. 1269-1271
Identification Number:	10.1109/LED.2011.2159476
Status:	Peer Reviewed
Publication Status:	Published
Access rights to Published version:	Restricted or Subscription Access
Funder:	Advantage West Midlands (AWM), Birmingham Science City
References:	[1] Shinohara, “Analysis of Power Losses in MOSFET Synchronous Rectifiers by using Their Design Parameters”, in Proc of ISPSD, pp.347-350, 1998. [2] R Hueting, E Hijzen, A Heringa, A Ludikhuize and M Zandt, “Gate- Drain Charge Analysis for Switching in Power Trench MOSFETs”, IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1323-1330, 2004. [3] M Darwish, C Yue, K Lui, F Giles, B Chan, K Chen, D Pattanayak, Q Chen, K Terrill and K Owyang, “A New Power W-Gated Trench MOSFET (WMOSFET) with High Switching Performance”, ISPSD, pp.24-27, 2003. [4] J Baliga, “Fundamentals of Power Semiconductor Devices”, Springer, 2008. [5] O Alatise, I Kennedy, K Heppenstall, G Petkos, K Khan, A Koh, J Parkin and P Rutter, “The Impact of Repetitive Unclamped Inductive Switching on the Electrical Performance of Low Voltage Discrete Power Trench MOSFETs”, IEEE Transactions on Electron Devices, vol. 57, no 7, pp.1651-1658, 2010.
URI:	http://wrap.warwick.ac.uk/id/eprint/38366