Shah, V. A., Dobbie, A. (Andrew), Myronov, Maksym and Leadley, D. R. (David R.) (2011) High quality relaxed Ge layers grown directly on a Si(001) substrate. Solid-State Electronics, Vol.62 (No.1). pp. 189-194. doi:10.1016/j.sse.2011.03.005

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Abstract

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10(8) cm(-2)) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 mu m thick (Hartmann et al. (2009) [4]).

We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.

Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 degrees C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10(8)-10(9) cm(-2), that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 degrees C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10(7) cm(-2), but at a cost of a significantly roughened surface.

Item Type:	Journal Article
Subjects:	Q Science > QC Physics Q Science > QD Chemistry
Divisions:	Faculty of Science > Physics
Library of Congress Subject Headings (LCSH):	Germanium, Silicon, Epitaxy, Semiconductors -- Surfaces, Semiconductors -- Materials
Journal or Publication Title:	Solid-State Electronics
Publisher:	Elsevier
ISSN:	0038-1101
Official Date:	August 2011
Dates:	Date Event August 2011 Published
Volume:	Vol.62
Number:	No.1
Page Range:	pp. 189-194
DOI:	10.1016/j.sse.2011.03.005
Status:	Peer Reviewed
Publication Status:	Published
Access rights to Published version:	Restricted or Subscription Access
Funder:	European Commission (EC), Engineering and Physical Sciences Research Council (EPSRC)
Grant number:	216171 (EC)

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