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Paterson, Michael S. and Zwick, Uri (1990) Shallow multiplication circuits. University of Warwick. Department of Computer Science. (Department of Computer Science research report). (Unpublished)
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PDF (Department of Computer Science Research Report)
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Abstract
Ofman, Wallace and others used carry save adders to design multiplication circuits whose total delay is proportional to the logarithm of the length of the two numbers multiplied. An extension of their work is presented here. The first part presents a general theory describing the optimal way in which given carry save adders can be combined into carry save networks. In the second part, two new designs of basic carry save adders are described. Using these building blocks and the above general theory, the shallowest know theoretical circuits for multiplication are obtained.
Item Type: | Report | ||||
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Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software | ||||
Divisions: | Faculty of Science, Engineering and Medicine > Science > Computer Science | ||||
Library of Congress Subject Headings (LCSH): | Computer arithmetic and logic units | ||||
Series Name: | Department of Computer Science research report | ||||
Publisher: | University of Warwick. Department of Computer Science | ||||
Official Date: | December 1990 | ||||
Dates: |
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Number: | Number 169 | ||||
Number of Pages: | 10 | ||||
DOI: | CS-RR-169 | ||||
Institution: | University of Warwick | ||||
Theses Department: | Department of Computer Science | ||||
Status: | Not Peer Reviewed | ||||
Publication Status: | Unpublished | ||||
Reuse Statement (publisher, data, author rights): | Michael Paterson and Uri Zwick, “Shallow Circuits and Concise Formulae for Multiple Addition and Multiplication”, <i>Computational Complexity</i> <b>3</b>(3), pp. 262-291 (1993) | ||||
Funder: | European Strategic Programme of Research and Development in Information Technology (ESPRIT) | ||||
Grant number: | 3075 (ESPRIT) | ||||
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