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Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts

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Mohalik, Swarup, Rajeev, A. C., Dixit, Manoj G., Ramesh, S., Pasupuleti, Vijay S., Pandya, Paritosh K. and Jiang, Shengbing (2008) Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. In: 45th annual Design Automation Conference, Anaheim, CA, USA. Published in: Proceedings of the 45th annual Design Automation Conference pp. 296-299. ISBN 9781605581156. doi:10.1145/1391469.1391544

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Official URL: http://dx.doi.org/10.1145/1391469.1391544

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Abstract

End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In this paper we give a formal definition of end-to-end latency, and use this as the basis for checking whether a stipulated deadline is violated within a bounded time. For unbounded verification, we model the system as a set of communicating Timed Automata, and perform reachability analysis. The proposed method takes into account the drift of clocks which is shown to affect the latency appreciably. The method has been tested on a medium sized automotive example.

Item Type: Conference Item (Paper)
Divisions: Faculty of Science, Engineering and Medicine > Engineering > WMG (Formerly the Warwick Manufacturing Group)
Journal or Publication Title: Proceedings of the 45th annual Design Automation Conference
ISBN: 9781605581156
Book Title: Proceedings of the 45th annual conference on Design automation - DAC '08
Official Date: 2008
Dates:
DateEvent
2008Modified
Page Range: pp. 296-299
DOI: 10.1145/1391469.1391544
Status: Peer Reviewed
Publication Status: Published
Conference Paper Type: Paper
Title of Event: 45th annual Design Automation Conference
Type of Event: Conference
Location of Event: Anaheim, CA, USA
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