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Compact electrothermal reliability modeling and experimental characterization of bipolar latchup in SiC and CoolMOS power MOSFETs
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Bonyadi, Roozbeh, Alatise, Olayiwola M., Jahdi, Saeed, Hu, Ji, Ortiz Gonzalez, Jose Angel, Ran, Li and Mawby, P. A. (2015) Compact electrothermal reliability modeling and experimental characterization of bipolar latchup in SiC and CoolMOS power MOSFETs. IEEE Transactions on Power Electronics, 30 (12). pp. 6978-6992. doi:10.1109/TPEL.2015.2388512 ISSN 0885-8993.
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WRAP_tpel-reg-2014-05-0717.r2.pdf - Accepted Version - Requires a PDF viewer. Download (2507Kb) | Preview |
Official URL: http://dx.doi.org/10.1109/TPEL.2015.2388512
Abstract
In this paper, a compact dynamic and fully coupled electrothermal model for parasitic BJT latchup is presented and validated by measurements. The model can be used to enhance the reliability of the latest generation of commercially available power devices. BJT latchup can be triggered by body-diode reverse-recovery hard commutation with high dV/dt or from avalanche conduction during unclamped inductive switching. In the case of body-diode reverse recovery, the base current that initiates BJT latchup is calculated from the solution of the ambipolar diffusion equation describing the minority carrier distribution in the antiparallel p-i-n body diode. For hard commutation with high dV/dt, the displacement current of the drain-body charging capacitance is critical for BJT latchup, whereas for avalanche conduction, the base current is calculated from impact ionization. The parasitic BJT is implemented in Simulink using the Ebers-Moll model and the temperature is calculated using a thermal network matched to the transient thermal impedance characteristic of the devices. This model has been applied to CoolMOS and SiC MOSFETs. Measurements show that the model correctly predicts BJT latchup during reverse recovery as a function of forward-current density and temperature. The model presented, when calibrated correctly by device manufacturers and applications engineers, is capable of benchmarking the robustness of power MOSFETs.
| Item Type: | Journal Article | ||||||
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| Subjects: | Q Science > QC Physics T Technology > TK Electrical engineering. Electronics Nuclear engineering |
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| Divisions: | Faculty of Science, Engineering and Medicine > Engineering > Engineering | ||||||
| Library of Congress Subject Headings (LCSH): | Electric inverters, Metal oxide semiconductor field-effect transistors , Bipolar transistors | ||||||
| Journal or Publication Title: | IEEE Transactions on Power Electronics | ||||||
| Publisher: | IEEE | ||||||
| ISSN: | 0885-8993 | ||||||
| Official Date: | December 2015 | ||||||
| Dates: |
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| Volume: | 30 | ||||||
| Number: | 12 | ||||||
| Page Range: | pp. 6978-6992 | ||||||
| DOI: | 10.1109/TPEL.2015.2388512 | ||||||
| Status: | Peer Reviewed | ||||||
| Publication Status: | Published | ||||||
| Access rights to Published version: | Restricted or Subscription Access | ||||||
| Copyright Holders: | IEEE | ||||||
| Date of first compliant deposit: | 4 December 2015 | ||||||
| Date of first compliant Open Access: | 24 June 2016 | ||||||
| Funder: | Engineering and Physical Sciences Research Council (EPSRC) | ||||||
| Grant number: | EP/K034804/1 |
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