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Mapping for maximum performance on FPGA DSP blocks
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Ronak, Bajaj and Fahmy, Suhaib A. (2016) Mapping for maximum performance on FPGA DSP blocks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35 (4). pp. 573-585. doi:10.1109/TCAD.2015.2474363
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Official URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?...
Abstract
The digital signal processing (DSP) blocks on modern field programmable gate arrays (FPGAs) are highly capable and support a variety of different datapath configurations. Unfortunately, inference in synthesis tools can fail to result in circuits that reach maximum DSP block throughput. We have developed a tool that maps graphs of add/sub/mult nodes to DSP blocks on Xilinx FPGAs, ensuring maximum throughput. This is done by delaying scheduling until after the graph has been partitioned onto DSP blocks and scheduled based on their pipeline structure, resulting in a throughput optimized implementation. Our tool prepares equivalent implementations in a variety of other methods, including high-level synthesis (HLS) for comparison. We show that the proposed approach offers an improvement in frequency of 100% over standard pipelined code, and 23% over Vivado HLS synthesis implementation, while retaining code portability, at the cost of a modest increase in logic resource usage.
| Item Type: | Journal Article | ||||||
|---|---|---|---|---|---|---|---|
| Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TK Electrical engineering. Electronics Nuclear engineering |
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| Divisions: | Faculty of Science > Engineering | ||||||
| Library of Congress Subject Headings (LCSH): | Signal processing -- Digital techniques, Field programmable gate arrays | ||||||
| Journal or Publication Title: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | ||||||
| Publisher: | IEEE | ||||||
| ISSN: | 0278-0070 | ||||||
| Official Date: | April 2016 | ||||||
| Dates: |
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| Date of first compliant deposit: | 31 March 2016 | ||||||
| Volume: | 35 | ||||||
| Number: | 4 | ||||||
| Number of Pages: | 12 | ||||||
| Page Range: | pp. 573-585 | ||||||
| DOI: | 10.1109/TCAD.2015.2474363 | ||||||
| Status: | Peer Reviewed | ||||||
| Publication Status: | Published | ||||||
| Adapted As: |
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