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Initiation interval aware resource sharing for FPGA DSP blocks

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Ronak, Bajaj and Fahmy, Suhaib A. (2016) Initiation interval aware resource sharing for FPGA DSP blocks. In: IEEE International Symposium on Field-Programmable Custom Computing Machines, Washington, DC, 1–3 May 2016. Published in: 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), p. 135.

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Official URL: http://dx.doi.org/10.1109/FCCM.2016.40

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Abstract

Resource sharing attempts to minimise usage of hardware blocks by mapping multiple operations onto same block at the cost of an increase in schedule length and initiation interval (II). Sharing multi-cycle high-throughput DSP blocks using traditional approaches results in significantly high II, determined by structure of dataflow graph of the design, thus limiting achievable throughput. We have developed a resource sharing technique that minimises the number of DSP blocks and schedule length given an II constraint.

Item Type: Conference Item (Poster)
Subjects: Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Science, Engineering and Medicine > Engineering > Engineering
Library of Congress Subject Headings (LCSH): Field programmable gate arrays , Signal processing--Digital techniques
Journal or Publication Title: 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM),
Publisher: IEEE
Official Date: 18 August 2016
Dates:
DateEvent
18 August 2016Published
1 March 2016Accepted
Page Range: p. 135
Status: Peer Reviewed
Publication Status: Published
Conference Paper Type: Poster
Title of Event: IEEE International Symposium on Field-Programmable Custom Computing Machines
Type of Event: Conference
Location of Event: Washington, DC
Date(s) of Event: 1–3 May 2016
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