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Are coarse-grained overlays ready for general purpose application acceleration on FPGAs?
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Jain, Abhishek Kumar, Maskell, Douglas L. and Fahmy, Suhaib A. (2016) Are coarse-grained overlays ready for general purpose application acceleration on FPGAs? In: IEEE International Conference on Pervasive Intelligence and Computing, Auckland, New Zealand, 8–12 Aug 2016. Published in: 2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech) ISBN 9781509040667. doi:10.1109/DASC-PICom-DataCom-CyberSciTec.2016.110
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Official URL: https://doi.org/10.1109/DASC-PICom-DataCom-CyberSc...
Abstract
Combining processors with hardware accelerators has become a norm with systems-on-chip (SoCs) ever present in modern compute devices. Heterogeneous programmable system on chip platforms sometimes referred to as hybrid FPGAs, tightly couple general purpose processors with high performance reconfigurable fabrics, providing a more flexible alternative. We can now think of a software application with hardware accelerated portions that are reconfigured at runtime. While such ideas have been explored in the past, modern hybrid FPGAs are the first commercial platforms to enable this move to a more software oriented view, where reconfiguration enables hardware resources to be shared by multiple tasks in a bigger application. However, while the rapidly increasing logic density and more capable hard resources found in modern hybrid FPGA devices should make them widely deployable, they remain constrained within specialist application domains. This is due to both design productivity issues and a lack of suitable hardware abstraction to eliminate the need for working with platform-specific details, as server and desktop virtualization has done in a more general sense. To allow mainstream adoption of FPGA based accelerators in general purpose computing, there is a need to virtualize FPGAs and make them more accessible to application developers who are accustomed to software API abstractions and fast development cycles. In this paper, we discuss the role of overlay architectures in enabling general purpose FPGA application acceleration.
Item Type: | Conference Item (Paper) | ||||||
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Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TK Electrical engineering. Electronics Nuclear engineering |
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Divisions: | Faculty of Science, Engineering and Medicine > Engineering > Engineering | ||||||
Library of Congress Subject Headings (LCSH): | Field programmable gate arrays, Systems on a chip, Heterogeneous computing, High performance processors , Computer architecture | ||||||
Journal or Publication Title: | 2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech) | ||||||
Publisher: | IEEE | ||||||
ISBN: | 9781509040667 | ||||||
Official Date: | 13 October 2016 | ||||||
Dates: |
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DOI: | 10.1109/DASC-PICom-DataCom-CyberSciTec.2016.110 | ||||||
Status: | Peer Reviewed | ||||||
Publication Status: | Published | ||||||
Access rights to Published version: | Open Access (Creative Commons) | ||||||
Date of first compliant deposit: | 29 June 2016 | ||||||
Conference Paper Type: | Paper | ||||||
Title of Event: | IEEE International Conference on Pervasive Intelligence and Computing | ||||||
Type of Event: | Conference | ||||||
Location of Event: | Auckland, New Zealand | ||||||
Date(s) of Event: | 8–12 Aug 2016 | ||||||
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