Skip to content Skip to navigation
University of Warwick
  • Study
  • |
  • Research
  • |
  • Business
  • |
  • Alumni
  • |
  • News
  • |
  • About

University of Warwick
Publications service & WRAP

Highlight your research

  • WRAP
    • Home
    • Search WRAP
    • Browse by Warwick Author
    • Browse WRAP by Year
    • Browse WRAP by Subject
    • Browse WRAP by Department
    • Browse WRAP by Funder
    • Browse Theses by Department
  • Publications Service
    • Home
    • Search Publications Service
    • Browse by Warwick Author
    • Browse Publications service by Year
    • Browse Publications service by Subject
    • Browse Publications service by Department
    • Browse Publications service by Funder
  • Help & Advice
University of Warwick

The Library

  • Login
  • Admin

An investigation of temperature sensitive electrical parameters for SiC power MOSFETs

Tools
- Tools
+ Tools

Ortiz Gonzalez, Jose Angel, Alatise, Olayiwola M., Hu, Ji, Ran, Li and Mawby, P. A. (Philip A.) (2017) An investigation of temperature sensitive electrical parameters for SiC power MOSFETs. IEEE Transactions on Power Electronics, 32 (10). 7954 -7966. doi:10.1109/TPEL.2016.2631447 ISSN 0885-8993.

[img] PDF
WRAP_engineering-160117-tpel2631447_for_grant_requirements.pdf - Accepted Version - Requires a PDF viewer.

Download (3862Kb)
Official URL: http://dx.doi.org/10.1109/TPEL.2016.2631447

Request Changes to record.

Abstract

This paper examines dynamic Temperature Sensitive Electrical Parameters (TSEPs) for SiC MOSFETs. It is shown that the output current switching rate (dIDS/dt) coupled with the gate current plateau (IGP) during turn-ON would be the most effective under specific operating conditions. Both parameters increase with the junction temperature of the device as a result of the negative temperature coefficient of the threshold voltage. The temperature dependency of dIDS/dt has been shown to increase with the device current rating (due to larger input capacitance) and external gate resistance (RGEXT). However, as dIDS/dt is increased by using a small RGEXT, parasitic inductance suppresses the temperature sensitivity of the drain and gate current transients by reducing the “effective gate voltage” on the device. Since the temperature sensitivity of dIDS/dt is at the highest with maximum RGEXT, there is a penalty from higher switching losses when this method is used in real time for junction temperature sensing. This paper investigates and models the temperature dependency of the gate and drain current transients as well as the compromise between the increased switching loss and the potential to implement effective condition monitoring using the evaluated TSEPs.

Item Type: Journal Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Science, Engineering and Medicine > Engineering > Engineering
Library of Congress Subject Headings (LCSH): Metal oxide semiconductor field-effect transistors , Silicon carbide -- Thermomechanical properties
Journal or Publication Title: IEEE Transactions on Power Electronics
Publisher: IEEE
ISSN: 0885-8993
Official Date: October 2017
Dates:
DateEvent
October 2017Published
22 November 2016Available
10 November 2016Accepted
Volume: 32
Number: 10
Page Range: 7954 -7966
DOI: 10.1109/TPEL.2016.2631447
Status: Peer Reviewed
Publication Status: Published
Access rights to Published version: Restricted or Subscription Access
Date of first compliant deposit: 19 January 2017
Date of first compliant Open Access: 19 January 2017
Funder: Engineering and Physical Sciences Research Council (EPSRC)
Grant number: EP/L007010/1 ; EP/K034804/1
Is Part Of:

Request changes or add full text files to a record

Repository staff actions (login required)

View Item View Item

Downloads

Downloads per month over past year

View more statistics

twitter

Email us: wrap@warwick.ac.uk
Contact Details
About Us