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Multipumping flexible DSP blocks for resource reduction on Xilinx FPGAs
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Ronak, Bajaj and Fahmy, Suhaib A. (2017) Multipumping flexible DSP blocks for resource reduction on Xilinx FPGAs. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 36 (9). 1471 -1482. doi:10.1109/TCAD.2016.2629421
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Official URL: http://doi.org/10.1109/TCAD.2016.2629421
Abstract
For complex datapaths, resource sharing can help reduce area consumption. Traditionally, resource sharing is applied when the same resource can be scheduled for different uses in different cycles, often resulting in a longer schedule. Multipumping is a method whereby a resource is clocked at a frequency that is a multiple of the surrounding circuit, thereby offering multiple executions per global clock cycle. This allows a single resource to be shared among multiple uses in the same cycle. This concept maps well to modern field-programmable gate arrays (FPGAs), where hard macro blocks are typically capable of running at higher frequencies than most designs implemented in the logic fabric. While this technique has been demonstrated for static resources, modern digital signal processing (DSP) blocks are flexible, supporting varied operations at runtime. In this paper, we demonstrate multipumping for resource sharing of the flexible DSP48E1 macros in Xilinx FPGAs. We exploit their dynamic programmability to enable resource sharing for the full set of supported DSP block operations, and compare this to multipumping only multipliers and DSP blocks with fixed configurations. The proposed approach saves on average 48% DSP blocks at a cost of 74% more LUTs, effectively saving 30% equivalent LUT area and is feasible for the majority of designs, in which clock frequency is typically below half the maximum supported by the DSP blocks.
| Item Type: | Journal Article | ||||||||
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| Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TK Electrical engineering. Electronics Nuclear engineering |
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| Divisions: | Faculty of Science > Engineering | ||||||||
| Library of Congress Subject Headings (LCSH): | Signal processing -- Digital techniques, Field programmable gate arrays | ||||||||
| Journal or Publication Title: | IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems | ||||||||
| Publisher: | IEEE | ||||||||
| ISSN: | 0278-0070 | ||||||||
| Official Date: | September 2017 | ||||||||
| Dates: |
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| Date of first compliant deposit: | 2 February 2017 | ||||||||
| Volume: | 36 | ||||||||
| Number: | 9 | ||||||||
| Page Range: | 1471 -1482 | ||||||||
| DOI: | 10.1109/TCAD.2016.2629421 | ||||||||
| Status: | Peer Reviewed | ||||||||
| Publication Status: | Published | ||||||||
| Access rights to Published version: | Restricted or Subscription Access |
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