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ZyCAP : efficient partial reconfiguration management on the Xilinx Zynq
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Vipin, Kizheppatt and Fahmy, Suhaib A. (2014) ZyCAP : efficient partial reconfiguration management on the Xilinx Zynq. IEEE Embedded Systems Letters, 6 (3). pp. 41-44. doi:10.1109/LES.2014.2314390
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Official URL: http://dx.doi.org/10.1109/LES.2014.2314390
Abstract
New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.
| Item Type: | Journal Article | ||||||
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| Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TK Electrical engineering. Electronics Nuclear engineering |
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| Divisions: | Faculty of Science > Engineering | ||||||
| Library of Congress Subject Headings (LCSH): | Field programmable gate arrays, Adaptive computing systems | ||||||
| Journal or Publication Title: | IEEE Embedded Systems Letters | ||||||
| Publisher: | IEEE | ||||||
| ISSN: | 1943-0663 | ||||||
| Official Date: | September 2014 | ||||||
| Dates: |
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| Volume: | 6 | ||||||
| Number: | 3 | ||||||
| Page Range: | pp. 41-44 | ||||||
| DOI: | 10.1109/LES.2014.2314390 | ||||||
| Status: | Peer Reviewed | ||||||
| Publication Status: | Published | ||||||
| Access rights to Published version: | Restricted or Subscription Access |
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