UNSPECIFIED (2003) Complexity and approximability results for slicing floorplan designs. EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, 149 (3). pp. 533-539. ISSN 0377-2217

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Abstract

The first stage in hierarchical approaches to floorplan design determines certain topological relations between the positions of indivisible cells on a VLSI chip. Various optimizations are then performed on this initial layout to minimize certain cost measures such as the chip area. We consider optimization problems in fixing the orientations of the cells and simultaneously fixing the directions of the cuts that are specified by a given slicing tree; the goal is to minimize the area of the chip. We prove that these problems are NP-hard in the ordinary sense, and we describe a pseudo-polynomial time algorithm for them. We also present fully polynomial time approximation schemes for these problems. (C) 2002 Elsevier Science B.V. All rights reserved.

Item Type:	Journal Article
Subjects:	H Social Sciences > HD Industries. Land use. Labor > HD28 Management. Industrial Management
Journal or Publication Title:	EUROPEAN JOURNAL OF OPERATIONAL RESEARCH
Publisher:	ELSEVIER SCIENCE BV
ISSN:	0377-2217
Date:	16 September 2003
Volume:	149
Number:	3
Number of Pages:	7
Page Range:	pp. 533-539
Publication Status:	Published
URI:	http://wrap.warwick.ac.uk/id/eprint/9643

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