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Design, simulation and fabrication of 4H-SiC Power MOSFETs
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Dai, Tianxiang (2018) Design, simulation and fabrication of 4H-SiC Power MOSFETs. PhD thesis, University of Warwick.
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WRAP_Theses_Dai_2018.pdf - Submitted Version - Requires a PDF viewer. Download (5Mb) | Preview |
Official URL: http://webcat.warwick.ac.uk/record=b3442140~S15
Abstract
For a 4H-SiC MOSFET to compete with Si counterparts, especially at lower voltages (1.2kV), the channel resistance contributes to a significant part in the total on-state resistance which must be addressed. Since most of the commercially available SiC wafer materials are grown on the {0001} crystal plane, a trench-gate MOSFET is necessary to take the advantage of the higher reported channel mobility on the {112 ̅ 0} crystal plane.
1.2kV trench MOSFET design and fabrication is the main focus in this work. The micro-trench free dry etching process has first been developed with a systematic study on the dry etching parameters. Trench corner rounding has also been investigated since a rounded corner is normally preferred to avoid an electric field hot spot. Two generations of trench MOSFETs have been designed and fabricated. The 1st generation devices have been used to validate the fabrication process. A maximum breakdown voltage of 1600V has been achieved for the 1st generation devices. The p+ trench bottom shielding region provides the protection for the trench gate oxide since it shifts the peak electric field from the oxide/semiconductor interface to a semiconductor p-n junction; however, it also introduces a parasitic JFET region into the trench MOSFET structure which severely degraded the on-state performance of the 1st generation devices. The 2nd generation devices were designed to eliminate the effect of the parasitic JFET region and improve the on-state performance. The optimised device structure with a current spreading layer (CSL) and p+ implantation clearance in the 2nd generation design has successfully eliminated the effect of the parasitic JFET region. Further design and process optimisation is necessary to increase the current density of the device which was as low as 3A/cm2. A fabrication trial has been carried out on the MOSFETs with integrated Schottky contacts at the termination region and therefore, external Schottky diodes are not necessary for many applications.
A 10kV DMOSFET has also been designed and fabricated with maximum breakdown voltage at 13.6kV. The high voltage termination design options have been discussed among the floating field ring (FFR) termination and the junction termination extensions (JTEs). The on-state performance is poor due to a photo mask error on the JFET length which needs to be optimised for the next generation devices.
Novel device structures have been studied with simulation. These include trench MOSFET with integrated Schottky diode and 3.3kV superjunction trench MOSFET. The MOSFET with integrated Schottky diode not only reduces the chip area consumption, but also reduces the chip count in the system level. In the proposed design, the Schottky contact is placed at the bottom of the trench structure for the first time. The superjunction structure has a great potential for SiC devices rated at above 3.3kV. The proposed design uses implanted p-pillar with a trench gate structure which combines the benefits of low channel resistance and low drift region resistance.
Item Type: | Thesis (PhD) | ||||
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Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering | ||||
Library of Congress Subject Headings (LCSH): | Metal oxide semiconductor field-effect transistors, Diodes, Schottky-barrier, Simulation, Engineering | ||||
Official Date: | September 2018 | ||||
Dates: |
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Institution: | University of Warwick | ||||
Theses Department: | School of Engineering | ||||
Thesis Type: | PhD | ||||
Publication Status: | Unpublished | ||||
Supervisor(s)/Advisor: | Mawby, Phil | ||||
Format of File: | |||||
Extent: | xvii, 163 leaves: illustrations, charts | ||||
Language: | eng |
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