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High-level FPGA accelerator design for structured-mesh-based explicit numerical solvers
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Kamalakkannan, K., Mudalige, Gihan R., Reguly, Istvan Z. and Fahmy, Suhaib A. (2021) High-level FPGA accelerator design for structured-mesh-based explicit numerical solvers. In: 35th IEEE International Parallel & Distributed Processing Symposium, Portland, Oregon, USA, 17-21 May 2021. Published in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) ISBN 9781665440660. doi:10.1109/IPDPS49936.2021.00117
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WRAP-high-level-FPGA-accelerator-design-structured-mesh-based-explicit-numerical-solvers-Mudalige-2020.pdf - Accepted Version - Requires a PDF viewer. Download (1296Kb) | Preview |
Official URL: https://doi.org/10.1109/IPDPS49936.2021.00117
Abstract
This paper presents a workflow for synthesizing near-optimal FPGA implementations of structured-mesh based stencil applications for explicit solvers. It leverages key characteristics of the application class and its computation-communication pattern and the architectural capabilities of the FPGA to accelerate solvers for high-performance computing applications. Key new features of the workflow are (1) the unification of standard state-of-the-art techniques with a number of high-gain optimizations such as batching and spatial blocking/tiling, motivated by increasing throughput for real-world workloads and (2) the development and use of a predictive analytical model to explore the design space, and obtain resource and performance estimates. Three representative applications are implemented using the design workflow on a Xilinx Alveo U280 FPGA, demonstrating near-optimal performance and over 85% predictive model accuracy. These are compared with equivalent highly-optimized implementations of the same applications on modern HPC-grade GPUs (Nvidia V100), analyzing time to solution, bandwidth, and energy consumption. Performance results indicate comparable runtimes with the V100 GPU, with over 2× energy savings for the largest non-trivial application on the FPGA. Our investigation shows the challenges of achieving high performance on current generation FPGAs compared to traditional architectures. We discuss determinants for a given stencil code to be amenable to FPGA implementation, providing insights into the feasibility and profitability of a design and its resulting performance.
Item Type: | Conference Item (Paper) | |||||||||
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Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering | |||||||||
Divisions: | Faculty of Science, Engineering and Medicine > Science > Computer Science Faculty of Science, Engineering and Medicine > Engineering > Engineering |
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Library of Congress Subject Headings (LCSH): | Field programmable gate arrays, Programmable array logic, Numerical analysis -- Data processing, Computer science -- Mathematics | |||||||||
Journal or Publication Title: | 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) | |||||||||
Publisher: | IEEE | |||||||||
ISBN: | 9781665440660 | |||||||||
Official Date: | 8 June 2021 | |||||||||
Dates: |
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DOI: | 10.1109/IPDPS49936.2021.00117 | |||||||||
Status: | Peer Reviewed | |||||||||
Publication Status: | Published | |||||||||
Re-use Statement: | © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||||||
Access rights to Published version: | Restricted or Subscription Access | |||||||||
Date of first compliant deposit: | 14 December 2020 | |||||||||
Date of first compliant Open Access: | 12 April 2021 | |||||||||
RIOXX Funder/Project Grant: |
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Conference Paper Type: | Paper | |||||||||
Title of Event: | 35th IEEE International Parallel & Distributed Processing Symposium | |||||||||
Type of Event: | Conference | |||||||||
Location of Event: | Portland, Oregon, USA | |||||||||
Date(s) of Event: | 17-21 May 2021 | |||||||||
Related URLs: |
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