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Build framework and runtime abstraction for partial reconfiguration on FPGA SoCs
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Bucknall, Alex R. (2022) Build framework and runtime abstraction for partial reconfiguration on FPGA SoCs. PhD thesis, University of Warwick.
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Official URL: http://webcat.warwick.ac.uk/record=b3821582
Abstract
Growth in edge computing has increased the requirement for edge systems to process larger volumes of real-time data, such as with image processing and machine learning; which are increasingly demanding of computing resources. Offloading tasks to the cloud provides some relief but is network dependant, high latency and expensive. Alternative architectures such as GPUs provide higher performance acceleration for this type of data processing but trade processing performance for an increase in power consumption. Another option is the Field Programmable Gate Array; a flexible matrix of logic that can be configured by a designer to provide a highly optimised computation path for incoming data. There are drawbacks; the FPGA design process is complex, the domain is dissimilar to software and the tools require bespoke expertise. A designer must manage the hardware to software paradigm introduced when tightly-coupled with general purpose processor. Advanced features, such as the ability to partially reconfigure (PR) specific regions of the FPGA, further increase this complexity. This thesis presents theory and demonstration of custom frameworks and tools for increasing abstraction and simplifying control over PR applications. We present mechanisms for networked PR; a mechanism for bypassing the traditional software networking stack to trigger PR with reduced latency and increased determinism. We developed a build framework for automating the end-to-end PR design process for Linux based systems as well as an abstracted runtime for managing the resulting applications. Finally, we take expand on this work and present a high level abstraction for PR on cyber physical systems, with a demonstration using the Robot Operating System. This work is released as open source contributions, designed to enable future PR research.
Item Type: | Thesis (PhD) | ||||
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Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software | ||||
Library of Congress Subject Headings (LCSH): | Field programmable gate arrays, Edge computing, Matrix logic, Intelligent control systems | ||||
Official Date: | January 2022 | ||||
Dates: |
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Institution: | University of Warwick | ||||
Theses Department: | School of Engineering | ||||
Thesis Type: | PhD | ||||
Publication Status: | Unpublished | ||||
Supervisor(s)/Advisor: | Fahmy, Suhaib | ||||
Sponsors: | Engineering and Physical Sciences Research Council | ||||
Format of File: | |||||
Extent: | xv, 159 leaves : illustrations | ||||
Language: | eng |
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