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VLSI design of a pipelined CORDIC processor
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Chown, Paul, Walton, D. W. and Nudd, G. R. (1990) VLSI design of a pipelined CORDIC processor. Coventry, UK: University of Warwick. Department of Computer Science. (Department of Computer Science Research Report). (Unpublished)
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Abstract
In this report we discuss the VLSI realisation of a pipelined CORDIC arithmetic unit to perform stable matrix row operations for the solution of systems of linear equations. The algorithmic considerations of the CORDIC process are highlighted and a chip level architecture is derived from these to implement the algorithm in a pipelined manner. We then proceed to give details of the 2pm CMOS processor that has been designed to implement that architecture.
| Item Type: | Report | ||||
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| Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software | ||||
| Divisions: | Faculty of Science > Computer Science | ||||
| Library of Congress Subject Headings (LCSH): | Microprocessors -- Design and construction | ||||
| Series Name: | Department of Computer Science Research Report | ||||
| Publisher: | University of Warwick. Department of Computer Science | ||||
| Place of Publication: | Coventry, UK | ||||
| Official Date: | October 1990 | ||||
| Dates: |
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| Number: | Number 164 | ||||
| Number of Pages: | 22 | ||||
| DOI: | CS-RR-164 | ||||
| Institution: | University of Warwick | ||||
| Theses Department: | Department of Computer Science | ||||
| Status: | Not Peer Reviewed | ||||
| Publication Status: | Unpublished | ||||
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