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A time-multiplexed FPGA overlay with linear interconnect
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Li, Xiangwei, Jain, Abhishek Kumar, Maskell, Douglas L. and Fahmy, Suhaib A. (2018) A time-multiplexed FPGA overlay with linear interconnect. In: Design Automation and Test in Europe Conference (DATE), Dresden, Germany, 19–23 Mar 2018. Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) doi:10.23919/DATE.2018.8342171
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WRAP-time-multiplexed-FPGA-overlay-interconnect-Fahmy-2017.pdf - Accepted Version - Requires a PDF viewer. Download (554Kb) | Preview |
Official URL: https://doi.org/10.23919/DATE.2018.8342171
Abstract
Coarse-grained overlays improve FPGA design pro- ductivity by providing fast compilation and software like pro- grammability. Soft processor based overlays with well-defined ISAs are attractive to application developers due to their ease of use. However, these overlays have significant FPGA resource overheads. Time multiplexed (TM) CGRA-like overlays represent an interesting alternative as they are able to change their behavior on a cycle by cycle basis while the compute kernel executes. This reduces the FPGA resource needed, but at the cost of a higher initiation interval (II) and hence reduced throughput.
The fully flexible routing network of current CGRA-like overlays results in high FPGA resource usage. However, many application kernels are acyclic and can be implemented using a much simpler linear feed-forward routing network. This paper examines a DSP block based TM overlay with linear interconnect where the overlay architecture takes account of the application kernels’ characteristics and the underlying FPGA architecture, so as to minimize the II and the FPGA resource usage. We examine a number of architectural extensions to the DSP block based functional unit to improve the II, throughput and latency. The results show an average 70% reduction in II, with corresponding improvements in throughput and latency.
Item Type: | Conference Item (Paper) | ||||||
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Subjects: | Q Science > QA Mathematics > QA76 Electronic computers. Computer science. Computer software T Technology > TK Electrical engineering. Electronics Nuclear engineering |
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Divisions: | Faculty of Science, Engineering and Medicine > Engineering > Engineering | ||||||
Library of Congress Subject Headings (LCSH): | Field programmable gate arrays -- Software, Routing (Computer network management) | ||||||
Journal or Publication Title: | 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) | ||||||
Publisher: | IEEE | ||||||
Official Date: | 23 April 2018 | ||||||
Dates: |
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DOI: | 10.23919/DATE.2018.8342171 | ||||||
Status: | Peer Reviewed | ||||||
Publication Status: | Published | ||||||
Re-use Statement: | © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | ||||||
Access rights to Published version: | Restricted or Subscription Access | ||||||
Date of first compliant deposit: | 1 December 2017 | ||||||
Date of first compliant Open Access: | 26 September 2018 | ||||||
Conference Paper Type: | Paper | ||||||
Title of Event: | Design Automation and Test in Europe Conference (DATE) | ||||||
Type of Event: | Conference | ||||||
Location of Event: | Dresden, Germany | ||||||
Date(s) of Event: | 19–23 Mar 2018 | ||||||
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