Warrier, Rakesh, Shreejith, Shanker, Zhang, Wei, Vun, Chan Hua and Fahmy, Suhaib A. (2017) Fracturable DSP block for multi-context reconfigurable architectures. Circuits, Systems, and Signal Processing, 36 (7). pp. 3020-3033. doi:10.1007/s00034-016-0445-x

PDF WRAP_cssp2016-warrier.pdf - Accepted Version - Requires a PDF viewer. Download (642Kb)

Request Changes to record.

Abstract

Multi-context architectures like NATURE enable low-power applications to leverage fast context switching for improved energy efficiency and lower area footprint. The NATURE architecture incorporates 16-bit reconfigurable DSP blocks for accelerating arithmetic computations, however, their fixed precision prevents efficient re-use in mixed-width arithmetic circuits. This paper presents an improved DSP block architecture for NATURE, with native support for temporal folding and run-time fracturability. The proposed DSP block can compute multiple sub-width operations in the same clock cycle and can dynamically switch between sub-width and full-width operations in different cycles. The NanoMap tool for mapping circuits onto NATURE is extended to exploit the fracturable multiplier unit incorporated in the DSP block. We demonstrate the efficiency of the proposed dynamically fracturable DSP block by implementing logic-intensive and compute-intensive benchmark applications. Our results illustrate that the fracturable DSP block can achieve a 53.7% reduction in DSP block utilization and a 42.5% reduction in area with a 122.5% reduction in power-delay product without exploiting logic folding. We also observe an average reduction of 6.43% in power-delay product for circuits that utilize NATURE’s temporal folding compared to the existing full precision DSP block in NATURE, leading to highly compact, energy efficient designs.

Item Type:	Journal Article
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:	Faculty of Science, Engineering and Medicine > Engineering > Engineering
Library of Congress Subject Headings (LCSH):	Signal processing -- Digital techniques
Journal or Publication Title:	Circuits, Systems, and Signal Processing
Publisher:	Springer
ISSN:	0278-081X
Official Date:	July 2017
Dates:	Date Event July 2017 Published 1 November 2016 Available 18 October 2016 Accepted
Volume:	36
Number:	7
Page Range:	pp. 3020-3033
DOI:	10.1007/s00034-016-0445-x
Status:	Peer Reviewed
Publication Status:	Published
Access rights to Published version:	Restricted or Subscription Access

Request changes or add full text files to a record

Repository staff actions (login required)

View Item

Downloads